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/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 1 argument
81 SYS_REG_ENC_NUM_CH(n) global() argument
82 SYS_REG_DEC_NUM_CH(n) global() argument
83 SYS_REG_ENC_RANK(n,ch) global() argument
84 SYS_REG_DEC_RANK(n,ch) global() argument
85 SYS_REG_ENC_COL(n,ch) global() argument
86 SYS_REG_DEC_COL(n,ch) global() argument
87 SYS_REG_ENC_BK(n,ch) global() argument
88 SYS_REG_DEC_BK(n,ch) global() argument
89 SYS_REG_ENC_CS0_ROW(n,ch) global() argument
90 SYS_REG_DEC_CS0_ROW(n,ch) global() argument
91 SYS_REG_ENC_CS1_ROW(n,ch) global() argument
92 SYS_REG_DEC_CS1_ROW(n,ch) global() argument
93 SYS_REG_ENC_BW(n,ch) global() argument
94 SYS_REG_DEC_BW(n,ch) global() argument
95 SYS_REG_ENC_DBW(n,ch) global() argument
96 SYS_REG_DEC_DBW(n,ch) global() argument
97 DDR_STRIDE(n) global() argument
[all...]
H A Dmisc_regs.h21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) argument
22 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) argument
/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.h13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) argument
14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) argument
15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) argument
16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ argument
20 SGRF_PMU_SLV_CON0_1(n) global() argument
21 SGRF_SLV_SECURE_CON0_4(n) global() argument
22 SGRF_DDRRGN_CON0_16(n) global() argument
23 SGRF_DDRRGN_CON20_34(n) global() argument
55 SGRF_L_MST_S_DDR_RGN(n) global() argument
57 SGRF_H_MST_S_DDR_RGN(n) global() argument
60 SGRF_PMU_CON(n) global() argument
66 STIMER0_CHN_BASE(n) global() argument
68 STIMER1_CHN_BASE(n) global() argument
[all...]
/arm-trusted-firmware/fdts/
H A Dfvp-defs-dynamiq.dtsi30 #define CPU(n, r) \ argument
41 #define THREAD(n) \ argument
46 #define CORE(n) \ argument
53 #define CORE(n) \ argument
68 CLUSTER(n) global() argument
85 CLUSTER(n) global() argument
106 CLUSTER(n) global() argument
131 CLUSTER(n) global() argument
160 CLUSTER(n) global() argument
193 CLUSTER(n) global() argument
230 CLUSTER(n) global() argument
271 CLUSTER(n) global() argument
[all...]
H A Dfvp-defs.dtsi34 #define CLS(n) (n / CPUS_PER_CLUSTER) argument
37 #define POS(n) (n % CPUS_PER_CLUSTER) argument
39 #define ADR(n, c, p) \ argument
61 #define CPU(n, c, p) \ argument
314 #define CORE(n) \ argument
321 CLUSTER(n) global() argument
326 CLUSTER(n) global() argument
333 CLUSTER(n) global() argument
341 CLUSTER(n) global() argument
[all...]
/arm-trusted-firmware/plat/allwinner/common/include/
H A Dsunxi_cpucfg_ncat.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
23 #define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) argument
25 #define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) argument
26 #define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BAS argument
27 SUNXI_ALT_RVBAR_HI_REG(n) global() argument
31 SUNXI_CPU_POWER_CLAMP_REG(c,n) global() argument
33 SUNXI_CPU_UNK_REG(n) global() argument
[all...]
H A Dsunxi_cpucfg_ncat2.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
/arm-trusted-firmware/include/drivers/rpi3/gpio/
H A Drpi3_gpio.h18 #define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04)) argument
19 #define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C)) argument
20 #define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28)) argument
21 #define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34)) argument
23 #define RPI3_GPIO_GPPUDCLK(n) (((n) * argument
[all...]
/arm-trusted-firmware/drivers/arm/gic/v2/
H A Dgicdv2_helpers.c23 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
34 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
45 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
56 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
67 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
78 unsigned int n = id >> ISACTIVER_SHIFT; gicd_read_isactiver() local
89 unsigned int n = id >> ICACTIVER_SHIFT; gicd_read_icactiver() local
100 unsigned int n = id >> IPRIORITYR_SHIFT; gicd_read_ipriorityr() local
111 unsigned int n = id >> ICFGR_SHIFT; gicd_read_icfgr() local
122 unsigned int n = id >> NSACR_SHIFT; gicd_read_nsacr() local
136 unsigned int n = id >> IGROUPR_SHIFT; gicd_write_igroupr() local
147 unsigned int n = id >> ISENABLER_SHIFT; gicd_write_isenabler() local
158 unsigned int n = id >> ICENABLER_SHIFT; gicd_write_icenabler() local
169 unsigned int n = id >> ISPENDR_SHIFT; gicd_write_ispendr() local
180 unsigned int n = id >> ICPENDR_SHIFT; gicd_write_icpendr() local
191 unsigned int n = id >> ISACTIVER_SHIFT; gicd_write_isactiver() local
202 unsigned int n = id >> ICACTIVER_SHIFT; gicd_write_icactiver() local
213 unsigned int n = id >> IPRIORITYR_SHIFT; gicd_write_ipriorityr() local
224 unsigned int n = id >> ICFGR_SHIFT; gicd_write_icfgr() local
235 unsigned int n = id >> NSACR_SHIFT; gicd_write_nsacr() local
[all...]
H A Dgicv2_helpers.c24 unsigned n = id >> ITARGETSR_SHIFT; in gicd_read_itargetsr() local
34 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_read_cpendsgir() local
44 unsigned n = id >> SPENDSGIR_SHIFT; in gicd_read_spendsgir() local
54 unsigned n = id >> ITARGETSR_SHIFT; in gicd_write_itargetsr() local
64 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_write_cpendsgir() local
74 unsigned n = id >> SPENDSGIR_SHIFT; gicd_write_spendsgir() local
[all...]
/arm-trusted-firmware/drivers/arm/gic/common/
H A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
80 unsigned int n = id >> ISACTIVER_SHIFT; gicd_read_isactiver() local
91 unsigned int n = id >> ICACTIVER_SHIFT; gicd_read_icactiver() local
102 unsigned int n = id >> IPRIORITYR_SHIFT; gicd_read_ipriorityr() local
113 unsigned int n = id >> ICFGR_SHIFT; gicd_read_icfgr() local
124 unsigned int n = id >> NSACR_SHIFT; gicd_read_nsacr() local
138 unsigned int n = id >> IGROUPR_SHIFT; gicd_write_igroupr() local
149 unsigned int n = id >> ISENABLER_SHIFT; gicd_write_isenabler() local
160 unsigned int n = id >> ICENABLER_SHIFT; gicd_write_icenabler() local
171 unsigned int n = id >> ISPENDR_SHIFT; gicd_write_ispendr() local
182 unsigned int n = id >> ICPENDR_SHIFT; gicd_write_icpendr() local
193 unsigned int n = id >> ISACTIVER_SHIFT; gicd_write_isactiver() local
204 unsigned int n = id >> ICACTIVER_SHIFT; gicd_write_icactiver() local
215 unsigned int n = id >> IPRIORITYR_SHIFT; gicd_write_ipriorityr() local
226 unsigned int n = id >> ICFGR_SHIFT; gicd_write_icfgr() local
237 unsigned int n = id >> NSACR_SHIFT; gicd_write_nsacr() local
[all...]
/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) argument
67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) argument
69 #define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4) argument
70 #define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4) argument
71 #define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * argument
73 GRF_SOC_CON(n) global() argument
74 GRF_SOC_STATUS(n) global() argument
75 GRF_CPU_STATUS(n) global() argument
76 GRF_OS_REG(n) global() argument
77 DDRGRF_SOC_CON(n) global() argument
78 DDRGRF_SOC_STATUS(n) global() argument
79 SGRF_SOC_CON(n) global() argument
80 SGRF_DMAC_CON(n) global() argument
81 SGRF_HDCP_KEY_CON(n) global() argument
[all...]
/arm-trusted-firmware/include/plat/arm/css/common/
H A Dcss_pm.h57 #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ argument
59 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
60 #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ argument
62 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
/arm-trusted-firmware/drivers/allwinner/
H A Dsunxi_msgbox.c22 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
23 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
25 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
28 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
31 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
[all...]
/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) argument
31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << argument
32 REFDIV(n) global() argument
33 PLL_LOCK(n) global() argument
46 CRU_CLKSEL_CON(n) global() argument
56 PMUCRU_GATE_CON(n) global() argument
57 CRU_GATE_CON(n) global() argument
147 PMUGRF_OSREG(n) global() argument
178 CRU_SOFTRST_CON(n) global() argument
192 CRU_CLKGATE_CON(n) global() argument
200 CRU_PMU_RSTHOLD_CON(n) global() argument
212 CRU_PMU_CLKGATE_CON(n) global() argument
227 PWM_CNT(n) global() argument
228 PWM_PERIOD_HPR(n) global() argument
229 PWM_DUTY_LPR(n) global() argument
230 PWM_CTRL(n) global() argument
262 GRF_SOC_CON(n) global() argument
272 PMUCRU_SOFTRST_CON(n) global() argument
[all...]
/arm-trusted-firmware/plat/imx/imx8m/ddr/
H A Ddram_retention.c20 #define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) argument
21 #define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n)) argument
22 #define CCM_TARGET_ROOT(n) (CCM_TARGET_ROOT_OFFSET + 0x80 * (n)) argument
[all...]
/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
32 #define FBDIV_ENC(n) ((n) << 16) argument
33 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) argument
34 #define POSTDIV2_ENC(n) ((n) << 1 argument
35 POSTDIV2_DEC(n) global() argument
36 POSTDIV1_ENC(n) global() argument
37 POSTDIV1_DEC(n) global() argument
38 REFDIV_ENC(n) global() argument
39 REFDIV_DEC(n) global() argument
45 PRESET_GPIO0_HOLD(n) global() argument
46 PRESET_GPIO1_HOLD(n) global() argument
[all...]
/arm-trusted-firmware/drivers/arm/gic/v3/
H A Dgic600ae_fmu_helpers.c31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \ argument
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr() argument
110 gic_fmu_read_errctlr(uintptr_t base,unsigned int n) gic_fmu_read_errctlr() argument
126 gic_fmu_read_errstatus(uintptr_t base,unsigned int n) gic_fmu_read_errstatus() argument
203 gic_fmu_write_errctlr(uintptr_t base,unsigned int n,uint64_t val) gic_fmu_write_errctlr() argument
212 gic_fmu_write_errstatus(uintptr_t base,unsigned int n,uint64_t val) gic_fmu_write_errstatus() argument
[all...]
/arm-trusted-firmware/plat/mediatek/mt8186/include/
H A Dsspm_reg.h18 #define STANDBYWFI_EN(n) (1 << (n + 8)) argument
19 #define GIC_IRQOUT_EN(n) (1 << (n + 0)) argument
/arm-trusted-firmware/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.h15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) argument
30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) argument
31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) argument
32 #define SGRF_CPU_CON(n) (0x40 + (n) * argument
33 SGRF_SOC_STATUS(n) global() argument
[all...]
/arm-trusted-firmware/plat/allwinner/common/
H A Dsunxi_cpu_ops.c23 #define SUNXI_C0_CPU_CTRL_REG(n) 0 argument
24 #define SUNXI_CPU_UNK_REG(n) 0 argument
25 #define SUNXI_CPU_CTRL_REG(n) 0 argument
H A Dsunxi_pm.c29 #define SUNXI_ALT_RVBAR_LO_REG(n) 0 argument
30 #define SUNXI_ALT_RVBAR_HI_REG(n) 0 argument
/arm-trusted-firmware/lib/libc/
H A Dsnprintf.c32 static void string_print(char **s, size_t n, size_t *chars_printed, in string_print() argument
41 static void unsigned_num_print(char **s, size_t n, size_t *chars_printed, in unsigned_num_print() argument
109 int vsnprintf(char *s, size_t n, const char *fmt, va_list args) in vsnprintf() argument
265 snprintf(char * s,size_t n,const char * fmt,...) snprintf() argument
[all...]
/arm-trusted-firmware/plat/allwinner/sun50i_a64/include/
H A Dsunxi_cpucfg.h22 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8) argument
23 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \ argument
/arm-trusted-firmware/include/drivers/auth/
H A Dauth_mod.h70 #define DEFINE_SIP_SP_PKG(n) DEFINE_SP_PKG(n, sip_sp_content_cert) argument
71 #define DEFINE_PLAT_SP_PKG(n) DEFINE_SP_PKG(n, plat_sp_content_cert) argument
73 #define DEFINE_SP_PKG(n, cert) \ argument

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