1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021 Sipeed 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_CPUCFG_H 8*91f16700Schasinglulu #define SUNXI_CPUCFG_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <sunxi_mmap.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* c = cluster, n = core */ 13*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010) 14*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014) 15*91f16700Schasinglulu #define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024) 16*91f16700Schasinglulu #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000) 19*91f16700Schasinglulu #define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000) 20*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) 21*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) 24*91f16700Schasinglulu #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) 25*91f16700Schasinglulu #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ 26*91f16700Schasinglulu (c) * 0x10 + (n) * 4) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0 29*91f16700Schasinglulu #define SUNXI_AA64nAA32_OFFSET 4 30*91f16700Schasinglulu 31*91f16700Schasinglulu static inline bool sunxi_cpucfg_has_per_cluster_regs(void) 32*91f16700Schasinglulu { 33*91f16700Schasinglulu return true; 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu #endif /* SUNXI_CPUCFG_H */ 37