1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MISC_REGS_H 8*91f16700Schasinglulu #define MISC_REGS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* CRU */ 11*91f16700Schasinglulu #define CRU_DPLL_CON0 0x40 12*91f16700Schasinglulu #define CRU_DPLL_CON1 0x44 13*91f16700Schasinglulu #define CRU_DPLL_CON2 0x48 14*91f16700Schasinglulu #define CRU_DPLL_CON3 0x4c 15*91f16700Schasinglulu #define CRU_DPLL_CON4 0x50 16*91f16700Schasinglulu #define CRU_DPLL_CON5 0x54 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* CRU_PLL_CON3 */ 19*91f16700Schasinglulu #define PLL_SLOW_MODE 0 20*91f16700Schasinglulu #define PLL_NORMAL_MODE 1 21*91f16700Schasinglulu #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) 22*91f16700Schasinglulu #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* PMU CRU */ 25*91f16700Schasinglulu #define PMU_CRU_GATEDIS_CON0 0x130 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* MISC_REGS_H */ 28