1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef CSS_PM_H 8*91f16700Schasinglulu #define CSS_PM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <cdefs.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <lib/psci/psci.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* SGI used to trigger per-core power down request */ 16*91f16700Schasinglulu #define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Macros to read the CSS power domain state */ 19*91f16700Schasinglulu #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] 20*91f16700Schasinglulu #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] 21*91f16700Schasinglulu 22*91f16700Schasinglulu static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) 23*91f16700Schasinglulu { 24*91f16700Schasinglulu #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 25*91f16700Schasinglulu return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; 26*91f16700Schasinglulu #else 27*91f16700Schasinglulu return 0; 28*91f16700Schasinglulu #endif 29*91f16700Schasinglulu } 30*91f16700Schasinglulu 31*91f16700Schasinglulu int css_pwr_domain_on(u_register_t mpidr); 32*91f16700Schasinglulu void css_pwr_domain_on_finish(const psci_power_state_t *target_state); 33*91f16700Schasinglulu void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state); 34*91f16700Schasinglulu void css_pwr_domain_off(const psci_power_state_t *target_state); 35*91f16700Schasinglulu void css_pwr_domain_suspend(const psci_power_state_t *target_state); 36*91f16700Schasinglulu void css_pwr_domain_suspend_finish( 37*91f16700Schasinglulu const psci_power_state_t *target_state); 38*91f16700Schasinglulu void __dead2 css_system_off(void); 39*91f16700Schasinglulu void __dead2 css_system_reset(void); 40*91f16700Schasinglulu void css_cpu_standby(plat_local_state_t cpu_state); 41*91f16700Schasinglulu void css_get_sys_suspend_power_state(psci_power_state_t *req_state); 42*91f16700Schasinglulu int css_node_hw_state(u_register_t mpidr, unsigned int power_level); 43*91f16700Schasinglulu void css_setup_cpu_pwr_down_intr(void); 44*91f16700Schasinglulu int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, 45*91f16700Schasinglulu void *handle, void *cookie); 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* 48*91f16700Schasinglulu * This mapping array has to be exported by the platform. Each element at 49*91f16700Schasinglulu * a given index maps that core to an SCMI power domain. 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[]; 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define SCMI_DOMAIN_ID_MASK U(0xFFFF) 54*91f16700Schasinglulu #define SCMI_CHANNEL_ID_MASK U(0xFFFF) 55*91f16700Schasinglulu #define SCMI_CHANNEL_ID_SHIFT U(16) 56*91f16700Schasinglulu 57*91f16700Schasinglulu #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ 58*91f16700Schasinglulu SCMI_CHANNEL_ID_SHIFT) 59*91f16700Schasinglulu #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) 60*91f16700Schasinglulu #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ 61*91f16700Schasinglulu SCMI_CHANNEL_ID_MASK) 62*91f16700Schasinglulu #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) 63*91f16700Schasinglulu 64*91f16700Schasinglulu #endif /* CSS_PM_H */ 65