1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_CPUCFG_H 8*91f16700Schasinglulu #define SUNXI_CPUCFG_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <sunxi_mmap.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* c = cluster, n = core */ 13*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10) 14*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10) 15*91f16700Schasinglulu #define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024) 16*91f16700Schasinglulu /* The T507 datasheet does not mention this register. */ 17*91f16700Schasinglulu #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4) 20*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) 21*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) 26*91f16700Schasinglulu #define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8) 27*91f16700Schasinglulu #define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) 30*91f16700Schasinglulu #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) 31*91f16700Schasinglulu #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ 32*91f16700Schasinglulu (c) * 0x10 + (n) * 4) 33*91f16700Schasinglulu #define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100) 36*91f16700Schasinglulu #define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104) 37*91f16700Schasinglulu #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) 38*91f16700Schasinglulu #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) 39*91f16700Schasinglulu 40*91f16700Schasinglulu #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 41*91f16700Schasinglulu #define SUNXI_AA64nAA32_OFFSET 24 42*91f16700Schasinglulu 43*91f16700Schasinglulu #endif /* SUNXI_CPUCFG_H */ 44