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Searched defs:ch (Results 1 – 25 of 33) sorted by relevance

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/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
77 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 1 argument
84 SYS_REG_DEC_RANK(n,ch) global() argument
85 SYS_REG_ENC_COL(n,ch) global() argument
86 SYS_REG_DEC_COL(n,ch) global() argument
87 SYS_REG_ENC_BK(n,ch) global() argument
88 SYS_REG_DEC_BK(n,ch) global() argument
89 SYS_REG_ENC_CS0_ROW(n,ch) global() argument
90 SYS_REG_DEC_CS0_ROW(n,ch) global() argument
91 SYS_REG_ENC_CS1_ROW(n,ch) global() argument
92 SYS_REG_DEC_CS1_ROW(n,ch) global() argument
93 SYS_REG_ENC_BW(n,ch) global() argument
94 SYS_REG_DEC_BW(n,ch) global() argument
95 SYS_REG_ENC_DBW(n,ch) global() argument
96 SYS_REG_DEC_DBW(n,ch) global() argument
[all...]
H A Daddressmap_shared.h91 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) argument
92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) argument
95 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) argument
96 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) argument
99 #define PHY_BASE(ch) (CTL_BASE(ch) argument
100 PHY_REG(ch,n) global() argument
102 MSCH_BASE(ch) global() argument
[all...]
/arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp/
H A Dbpmp.c24 static uint32_t channel_field(unsigned int ch) in channel_field() argument
29 static bool master_free(unsigned int ch) in master_free() argument
34 static bool master_acked(unsigned int ch) in master_acked() argument
39 static void signal_slave(unsigned int ch) in signal_slave() argument
44 free_master(unsigned int ch) free_master() argument
54 unsigned int ch = (unsigned int)plat_my_core_pos(); tegra_bpmp_send_receive_atomic() local
119 unsigned int ch; tegra_bpmp_init() local
[all...]
/arm-trusted-firmware/drivers/arm/css/scmi/
H A Dscmi_common.c29 void scmi_get_channel(scmi_channel_t *ch) in scmi_get_channel() argument
42 void scmi_send_sync_command(scmi_channel_t *ch) in scmi_send_sync_command() argument
77 void scmi_put_channel(scmi_channel_t *ch) in scmi_put_channel() argument
95 scmi_channel_t *ch = (scmi_channel_t *)p; scmi_proto_version() local
128 scmi_channel_t *ch = (scmi_channel_t *)p; scmi_proto_msg_attr() local
157 scmi_init(scmi_channel_t * ch) scmi_init() argument
[all...]
H A Dscmi_sys_pwr_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_set() local
56 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_get() local
[all...]
H A Dscmi_pwr_dmn_proto.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_set() local
65 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_get() local
[all...]
H A Dscmi_ap_core_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_set_reset_addr() local
57 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_get_reset_addr() local
[all...]
/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) in phy_pctrl_reset() argument
146 set_cs_training_index(uint32_t ch,uint32_t rank) set_cs_training_index() argument
156 select_per_cs_training_index(uint32_t ch,uint32_t rank) select_per_cs_training_index() argument
164 override_write_leveling_value(uint32_t ch) override_write_leveling_value() argument
184 data_training(uint32_t ch,struct rk3399_sdram_params * sdram_params,uint32_t training_flag) data_training() argument
434 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; set_ddrconfig() local
489 pctl_cfg(uint32_t ch,struct rk3399_sdram_params * sdram_params) pctl_cfg() argument
549 uint32_t ch, ch_count; dram_switch_to_next_index() local
701 uint32_t ch, byte, i; dmc_suspend() local
758 phy_dll_bypass_set(uint32_t ch,uint32_t freq) phy_dll_bypass_set() argument
[all...]
H A Ddram.c26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init() local
[all...]
/arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram.c342 #define foreach_vch(ch) \ argument
345 foreach_ech(ch) global() argument
624 uint32_t ch; reg_ddrphy_write_a() local
678 ddr_setval_s(uint32_t ch,uint32_t slice,uint32_t _regdef,uint32_t val) ddr_setval_s() argument
702 ddr_getval_s(uint32_t ch,uint32_t slice,uint32_t _regdef) ddr_getval_s() argument
726 ddr_setval(uint32_t ch,uint32_t regdef,uint32_t val) ddr_setval() argument
733 uint32_t ch; ddr_setval_ach_s() local
752 ddr_getval(uint32_t ch,uint32_t regdef) ddr_getval() argument
759 uint32_t ch; ddr_getval_ach() local
768 uint32_t ch, slice; ddr_getval_ach_as() local
853 uint32_t ch; ddrphy_regif_chk() local
1141 uint32_t ch; regif_pll_wa() local
1607 uint32_t ch, slice; ddr_config_sub() local
1741 get_ca_swizzle(uint32_t ch,uint32_t ddr_csn,uint32_t * p_swz) get_ca_swizzle() argument
1766 uint32_t ch, slice; ddr_config_sub_h3v1x() local
1855 uint32_t ch, slice; ddr_config() local
1998 uint32_t ch, csab; dbsc_regset_pre() local
2044 uint32_t ch; dbsc_regset() local
2345 uint32_t ch, cs; dbsc_regset_post() local
2525 uint32_t ch; dfi_init_start() local
2606 uint32_t ch; change_lpddr4_en() local
2632 uint32_t ch, index; set_term_code() local
2798 uint32_t ch; wait_freqchgreq() local
2830 uint32_t ch; set_freqchgack() local
2844 uint32_t ch; set_dfifrequency() local
2906 uint32_t ch; pi_training_go() local
2987 uint32_t ch, slice; init_ddr() local
3215 uint32_t ch; swlvl1() local
3265 wdqdm_clr1(uint32_t ch,uint32_t ddr_csn) wdqdm_clr1() argument
3293 wdqdm_ana1(uint32_t ch,uint32_t ddr_csn) wdqdm_ana1() argument
3372 uint32_t ch, slice; wdqdm_cp() local
3408 uint32_t ch, cs, slice; wdqdm_man1() local
3528 uint32_t datal, ch, ddr_csn, mr14_bkup[4][4]; wdqdm_man() local
3641 rdqdm_clr1(uint32_t ch,uint32_t ddr_csn) rdqdm_clr1() argument
3680 rdqdm_ana1(uint32_t ch,uint32_t ddr_csn) rdqdm_ana1() argument
3791 uint32_t ch; rdqdm_man1() local
3962 uint32_t ch, slice; rx_offset_cal() local
4025 uint32_t ch, slice; rx_offset_cal_hw() local
4074 uint32_t ch, slice; adjust_rddqs_latency() local
4115 uint32_t ch, cs, slice; adjust_wpath_latency() local
4148 uint32_t ch, cs; rcar_dram_init() local
4347 uint32_t ch; pvtcode_update() local
4416 uint32_t ch; pvtcode_update2() local
4434 uint32_t ch; ddr_padcal_tcompensate_getinit() local
[all...]
H A Dboot_init_dram_regdef.h31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
64 #define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) argument
/arm-trusted-firmware/lib/libc/
H A Dstrchr.c41 strchr(const char *p, int ch) in strchr() argument
H A Dstrrchr.c36 strrchr(const char *p, int ch) in strrchr() argument
H A Dprintf.c186 char ch = *fmt; in vprintf() local
H A Dsnprintf.c23 #define CHECK_AND_PUT_CHAR(buf, size, chars_printed, ch) \ argument
/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
H A Dbpmp.h22 #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
23 #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) argument
24 #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
/arm-trusted-firmware/drivers/renesas/common/
H A Dddr_regs.h16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
96 #define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) argument
101 #define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) argument
106 #define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) argument
111 #define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) argument
116 DBSC_DBPDCNT2(ch) global() argument
121 DBSC_DBPDCNT3(ch) global() argument
126 DBSC_DBPDLK(ch) global() argument
131 DBSC_DBPDRGA(ch) global() argument
132 DBSC_DBPDRGD(ch) global() argument
141 DBSC_DBPDSTAT(ch) global() argument
[all...]
/arm-trusted-firmware/drivers/arm/css/scmi/vendor/
H A Dscmi_sq.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_get_draminfo() local
/arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/
H A Divc.c75 volatile const struct ivc_channel_header *ch) in ivc_channel_empty() argument
106 volatile const struct ivc_channel_header *ch) in ivc_channel_full() argument
121 volatile const struct ivc_channel_header *ch) in ivc_channel_avail_count() argument
222 volatile const struct ivc_channel_header *ch, in ivc_frame_pointer() argument
[all...]
H A Dintf.c60 const struct ivc *ch = &ivc_ccplex_bpmp_channel; in tegra_bpmp_get_next_out_frame() local
/arm-trusted-firmware/services/spd/trusty/
H A Dgeneric-arm64-smcall.c40 static void trusty_dputc(char ch, int secure) in trusty_dputc() argument
/arm-trusted-firmware/drivers/arm/dcc/
H A Ddcc_console.c94 static int32_t dcc_console_putc(int32_t ch, struct console *console) in dcc_console_putc() argument
/arm-trusted-firmware/plat/socionext/synquacer/drivers/scp/
H A Dsq_scmi.c202 static int scmi_ap_core_init(scmi_channel_t *ch) in scmi_ap_core_init() argument
/arm-trusted-firmware/drivers/marvell/mochi/
H A Dapn806_setup.c70 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000) argument
H A Dap807_setup.c75 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000) argument

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