Lines Matching defs:ch
246 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
248 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
249 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
253 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
268 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
318 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
319 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
326 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
327 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
342 #define foreach_vch(ch) \
343 for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
345 #define foreach_ech(ch) \
346 for (ch = 0; ch < DRAM_CH_CNT; ch++)
624 uint32_t ch;
630 foreach_vch(ch) {
631 mmio_write_32(DBSC_DBPDRGA(ch), regadd);
635 foreach_vch(ch) {
636 mmio_write_32(DBSC_DBPDRGD(ch), regdata);
646 foreach_vch(ch) {
647 reg_ddrphy_write(ch, regadd, regdata);
678 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
697 tmp = reg_ddrphy_read(ch, adr);
699 reg_ddrphy_write(ch, adr, tmp);
702 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
720 tmp = reg_ddrphy_read(ch, adr);
726 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
728 ddr_setval_s(ch, 0, regdef, val);
733 uint32_t ch;
735 foreach_vch(ch)
736 ddr_setval_s(ch, slice, regdef, val);
752 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
754 return ddr_getval_s(ch, 0, regdef);
759 uint32_t ch;
761 foreach_vch(ch)
762 p[ch] = ddr_getval_s(ch, 0, regdef);
768 uint32_t ch, slice;
772 foreach_vch(ch)
774 *pp++ = ddr_getval_s(ch, slice, regdef);
853 uint32_t ch;
866 foreach_vch(ch) {
867 if (tmp_ach[ch] != PI_VERSION_CODE)
1141 uint32_t ch;
1215 foreach_vch(ch)
1216 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
1225 foreach_vch(ch)
1226 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
1229 foreach_ech(ch)
1230 if ((board_cnf->phyvalid) & BIT(ch))
1231 while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f)
1552 ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
1607 uint32_t ch, slice;
1613 foreach_vch(ch) {
1617 (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
1618 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
1619 board_cnf->ch[ch].dq_swap[slice]);
1620 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
1621 board_cnf->ch[ch].dm_swap[slice]);
1624 ddr_setval_s(ch, slice,
1629 ddr_setval_s(ch, slice,
1636 data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
1641 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
1642 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
1644 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
1645 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
1647 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
1650 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
1651 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
1652 ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
1659 data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
1662 tmp = board_cnf->ch[ch].ca_swap;
1668 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
1671 tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
1676 ddr_setval_s(ch, 2,
1679 ddr_setval_s(ch, 2,
1682 ddr_setval_s(ch, 2,
1685 ddr_setval_s(ch, 2,
1688 ddr_setval_s(ch, 2,
1692 ddr_setval_s(ch, 2,
1695 ddr_setval_s(ch, 2,
1698 ddr_setval_s(ch, 2,
1710 ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
1717 tmp = board_cnf->ch[ch].dqs_swap;
1724 data_l = board_cnf->ch[ch].dqs_swap;
1725 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
1726 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
1728 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
1730 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
1732 ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
1735 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
1737 ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
1741 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
1754 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
1758 tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
1766 uint32_t ch, slice;
1783 foreach_vch(ch) {
1787 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
1794 ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
1795 board_cnf->ch[ch].dq_swap[slice]);
1798 ddr_setval_s(ch, slice,
1803 ddr_setval_s(ch, slice,
1809 ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
1810 ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
1811 ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
1813 get_ca_swizzle(ch, 0, &ca_swizzle);
1815 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle);
1816 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000);
1817 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000);
1818 ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000);
1819 ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
1822 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
1824 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
1832 tmp = board_cnf->ch[ch].dq_swap[slice];
1846 ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
1855 uint32_t ch, slice;
1875 foreach_vch(ch) {
1879 tmp = board_cnf->ch[ch].wdqlvl_patt[i];
1884 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
1886 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
1888 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
1890 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
1892 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
1900 foreach_vch(ch) {
1902 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
1906 reg_ddrphy_write(ch,
1917 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
1921 reg_ddrphy_write(ch,
1933 (board_cnf->ch[ch].cacs_adj
1940 reg_ddrphy_write(ch,
1957 foreach_vch(ch) {
1962 _adj = board_cnf->ch[ch].dm_adj_w[slice];
1964 _adj = board_cnf->ch[ch].dq_adj_w[dq];
1966 ddr_setval_s(ch, slice,
1975 foreach_vch(ch) {
1980 _adj = board_cnf->ch[ch].dm_adj_r[slice];
1982 _adj = board_cnf->ch[ch].dq_adj_r[dq];
1984 ddr_setval_s(ch, slice,
1987 ddr_setval_s(ch, slice,
1998 uint32_t ch, csab;
2017 foreach_vch(ch) {
2019 mmio_write_32(DBSC_DBMEMCONF(ch, csab),
2026 foreach_ech(ch) {
2027 if ((ddr_phyvalid & (1U << ch)))
2028 data_l = (data_l & (~(0x000000FF << (ch * 8))))
2029 | (((board_cnf->ch[ch].dqs_swap & 0x0003)
2030 | ((board_cnf->ch[ch].dqs_swap & 0x0030)
2032 | ((board_cnf->ch[ch].dqs_swap & 0x0300)
2034 | ((board_cnf->ch[ch].dqs_swap & 0x3000)
2035 >> 6)) << (ch * 8));
2044 uint32_t ch;
2211 foreach_vch(ch) {
2212 data_l2 = data_l2 | (data_l << (4 * ch));
2345 uint32_t ch, cs;
2351 foreach_vch(ch) {
2353 if ((ch_have_this_cs[cs] & (1U << ch)) != 0) {
2355 ddr_setval_s(ch, slice,
2358 data_l = ddr_getval_s(ch, slice,
2394 foreach_ech(ch) {
2396 if (ddr_density[ch][cs] == 0xff) {
2397 mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00);
2399 mmio_write_32(DBSC_DBMEMCONF(ch, cs),
2400 DBMEMCONF_REGD(ddr_density[ch]
2404 mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000);
2405 mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000);
2525 uint32_t ch;
2545 foreach_vch(ch)
2546 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
2555 foreach_vch(ch)
2556 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
2566 foreach_vch(ch)
2567 mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
2574 foreach_vch(ch) {
2575 data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
2577 phytrainingok |= (1U << ch);
2586 /* all ch ok? */
2596 foreach_vch(ch)
2597 mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010);
2606 uint32_t ch;
2615 foreach_vch(ch) {
2617 data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
2623 ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
2632 uint32_t ch, index;
2679 foreach_vch(ch) {
2682 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
2687 foreach_vch(ch) {
2688 data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
2694 ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
2708 ddr_setval(ch,
2715 foreach_vch(ch) {
2719 ddr_getval(ch,
2722 ddr_setval(ch,
2798 uint32_t ch;
2810 foreach_vch(ch) {
2811 data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
2818 foreach_vch(ch) {
2819 data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
2830 uint32_t ch;
2838 foreach_vch(ch)
2839 mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
2844 uint32_t ch;
2847 foreach_vch(ch)
2848 mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
2850 foreach_vch(ch) {
2851 mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24,
2906 uint32_t ch;
2915 foreach_vch(ch)
2916 ddr_getval(ch, _reg_PI_INT_STATUS);
2955 foreach_vch(ch) {
2956 if (complete & (1U << ch))
2959 ddr_getval(ch, _reg_PI_INT_STATUS);
2961 complete |= (1U << ch);
2969 foreach_vch(ch) {
2971 data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
2972 data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
2973 ddr_setval(ch, _reg_PI_INT_ACK, data_l);
2987 uint32_t ch, slice;
2999 foreach_vch(ch)
3000 mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
3021 foreach_vch(ch)
3022 mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
3030 foreach_vch(ch)
3031 mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
3107 foreach_vch(ch) {
3108 data_l = ddr_getval(ch, _reg_PI_CS_MAP);
3109 if (!(ch_have_this_cs[1] & (1U << ch)))
3111 ddr_setval(ch, _reg_PI_CS_MAP, data_l);
3122 foreach_vch(ch) {
3124 ddr_setval_s(ch, slice,
3126 ((ch_have_this_cs[1]) >> ch)
3142 foreach_vch(ch) {
3144 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
3145 ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
3151 adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj
3154 ddr_setval_s(ch, 2,
3215 uint32_t ch;
3228 foreach_vch(ch) {
3229 if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) {
3230 ddr_setval(ch, reg_cs, ddr_csn);
3231 ddr_setval(ch, reg_kick, 0x01);
3234 foreach_vch(ch) {
3236 ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
3242 foreach_vch(ch) {
3243 if (!(waiting & (1U << ch)))
3245 data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
3247 waiting &= ~(1U << ch);
3265 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
3275 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3280 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch))
3281 wdqdm_dly[ch][cs][slice][i] =
3282 wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
3284 wdqdm_dly[ch][cs][slice][i] = data_l;
3285 wdqdm_le[ch][cs][slice][i] = 0;
3286 wdqdm_te[ch][cs][slice][i] = 0;
3288 wdqdm_st[ch][cs][slice] = 0;
3289 wdqdm_win[ch][cs][slice] = 0;
3293 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
3310 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3315 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
3319 _adj = board_cnf->ch[ch].dm_adj_w[slice];
3321 _adj = board_cnf->ch[ch].dq_adj_w[dq];
3325 ddr_getval_s(ch, slice,
3327 ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
3329 wdqdm_dly[ch][cs][slice][i] = data_l;
3331 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
3332 data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
3333 wdqdm_st[ch][cs][slice] = data_l;
3336 ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
3340 ddr_getval_s(ch, slice,
3342 wdqdm_te[ch][cs][slice][i] = data_l;
3344 ddr_getval_s(ch, slice,
3346 wdqdm_le[ch][cs][slice][i] = data_l;
3348 (int32_t)wdqdm_te[ch][cs][slice][i] -
3349 wdqdm_le[ch][cs][slice][i];
3355 wdqdm_win[ch][cs][slice] = min_win;
3358 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
3361 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
3362 ((ch_have_this_cs[1]) >> ch) & 0x01);
3372 uint32_t ch, slice;
3377 foreach_vch(ch) {
3380 ddr_setval_s(ch, slice,
3384 if (!(ch_have_this_cs[1] & (1U << ch)))
3389 rdqdm_dly[ch][tgt_cs][slice]
3393 rdqdm_dly[ch][src_cs][slice]
3396 ddr_setval_s(ch, slice,
3408 uint32_t ch, cs, slice;
3420 foreach_vch(ch) {
3421 high_dq[ch] = 0;
3423 k = (board_cnf->ch[ch].dqs_swap >>
3426 high_dq[ch] |= (1U << slice);
3428 ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00);
3454 foreach_vch(ch) {
3455 data_l = mmio_read_32(DBSC_DBDFICNT(ch));
3459 k = (high_dq[ch] ^ 0x0f);
3461 k = high_dq[ch];
3463 mmio_write_32(DBSC_DBDFICNT(ch), data_l);
3464 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
3474 foreach_vch(ch) {
3476 ddr_getval(ch,
3478 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
3487 foreach_vch(ch) {
3488 mr14_csab0_bak[ch] =
3489 ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
3491 foreach_vch(ch) {
3492 ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
3493 mr14_csab0_bak[ch]);
3496 foreach_vch(ch) {
3497 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
3498 wdqdm_clr1(ch, ddr_csn);
3501 err = wdqdm_ana1(ch, ddr_csn);
3503 err_flg |= (1U << (ddr_csn * 4 + ch));
3514 foreach_vch(ch) {
3515 data_l = mmio_read_32(DBSC_DBDFICNT(ch));
3517 mmio_write_32(DBSC_DBDFICNT(ch), data_l);
3518 ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
3528 uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
3568 foreach_vch(ch) {
3570 mr14_bkup[ch][ddr_csn] =
3571 ddr_getval(ch,
3587 foreach_vch(ch) {
3589 mr14_bkup[ch][ddr_csn] =
3590 (mr14_bkup[ch][ddr_csn] +
3591 ddr_getval(ch,
3594 ddr_setval(ch,
3597 mr14_bkup[ch][ddr_csn]);
3641 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
3651 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3656 if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) {
3657 rdqdm_dly[ch][cs][slice][i] =
3658 rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
3659 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
3660 rdqdm_dly[ch][CS_CNT - 1 - cs][slice +
3664 rdqdm_dly[ch][cs][slice][i] = data_l;
3665 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
3668 rdqdm_le[ch][cs][slice][i] = 0;
3669 rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
3670 rdqdm_te[ch][cs][slice][i] = 0;
3671 rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0;
3672 rdqdm_nw[ch][cs][slice][i] = 0;
3673 rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0;
3675 rdqdm_st[ch][cs][slice] = 0;
3676 rdqdm_win[ch][cs][slice] = 0;
3680 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
3696 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3701 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
3704 ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
3710 _adj = board_cnf->ch[ch].dm_adj_r[slice];
3712 _adj = board_cnf->ch[ch].dq_adj_r[dq];
3717 ddr_getval_s(ch, slice,
3720 ddr_setval_s(ch, slice,
3723 rdqdm_dly[ch][cs][slice][i] = data_l;
3726 ddr_getval_s(ch, slice,
3729 ddr_setval_s(ch, slice,
3732 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
3737 ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
3738 rdqdm_st[ch][cs][slice] = data_l;
3739 rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
3747 ddr_setval_s(ch, slice,
3752 ddr_getval_s(ch, slice,
3754 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
3758 ddr_getval_s(ch, slice,
3760 rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
3764 ddr_getval_s(ch, slice,
3766 rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
3770 (int32_t)rdqdm_te[ch][cs][slice +
3773 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
3780 rdqdm_win[ch][cs][slice] = min_win;
3791 uint32_t ch;
3808 foreach_vch(ch) {
3809 if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
3810 rdqdm_clr1(ch, ddr_csn);
3814 err = rdqdm_ana1(ch, ddr_csn);
3820 foreach_vch(ch) {
3821 if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
3823 if (ddr_getval_s(ch, slice,
3826 err = (1U << ch) |
3839 adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
3841 adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
3842 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
3843 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
3844 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
3845 rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
3846 rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
3848 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
3849 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
3850 rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
3851 rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
3962 uint32_t ch, slice;
3970 foreach_vch(ch) {
3973 val[ch][slice][index] = 0;
3985 foreach_vch(ch) {
3987 tmp = tmp_ach_as[ch][slice];
3991 val[ch][slice][index] |=
3994 val[ch][slice][index] &=
4001 foreach_vch(ch) {
4005 tmpval = val[ch][slice][index];
4013 ddr_setval_s(ch, slice,
4025 uint32_t ch, slice;
4040 foreach_vch(ch)
4042 tmp_ach_as[ch][slice] =
4043 ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
4046 foreach_vch(ch) {
4048 tmp = tmp_ach_as[ch][slice];
4074 uint32_t ch, slice;
4080 foreach_vch(ch) {
4083 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX,
4087 ddr_getval_s(ch, slice,
4090 ddr_getval_s(ch, slice,
4103 ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE,
4104 ddr_getval_s(ch, slice,
4115 uint32_t ch, cs, slice;
4120 foreach_vch(ch) {
4123 ddr_setval_s(ch, slice,
4126 ddr_getval_s(ch, slice,
4129 ddr_getval_s(ch, slice,
4135 ddr_getval_s(ch, slice,
4137 ddr_setval_s(ch, slice,
4148 uint32_t ch, cs;
4226 /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */
4243 foreach_ech(ch)
4245 ddr_density[ch][cs] = 0xff;
4247 foreach_vch(ch) {
4249 data_l = board_cnf->ch[ch].ddr_density[cs];
4250 ddr_density[ch][cs] = data_l;
4259 ch_have_this_cs[cs] |= (1U << ch);
4329 foreach_vch(ch)
4330 mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
4347 uint32_t ch;
4352 foreach_vch(ch) {
4353 pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6;
4354 pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0;
4364 pvtn[ch] = pvtn_tmp + pvtn_init;
4365 pvtp[ch] = pvtp_tmp + pvtp_init;
4367 if (pvtn[ch] > 63) {
4368 pvtn[ch] = 63;
4369 pvtp[ch] =
4376 data_l = pvtp[ch] | (pvtn[ch] << 6) |
4377 (tcal.tcomp_cal[ch] & 0xfffff000);
4378 reg_ddrphy_write(ch,
4381 reg_ddrphy_write(ch,
4384 reg_ddrphy_write(ch,
4387 reg_ddrphy_write(ch,
4390 reg_ddrphy_write(ch,
4394 data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
4395 reg_ddrphy_write(ch,
4398 reg_ddrphy_write(ch,
4401 reg_ddrphy_write(ch,
4404 reg_ddrphy_write(ch,
4407 reg_ddrphy_write(ch,
4416 uint32_t ch;
4418 foreach_vch(ch) {
4419 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
4420 tcal.init_cal[ch] | 0x00020000);
4421 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
4422 tcal.init_cal[ch]);
4423 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
4424 tcal.init_cal[ch]);
4425 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
4426 tcal.init_cal[ch]);
4427 reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
4428 tcal.init_cal[ch]);
4434 uint32_t ch;
4439 for (ch = 0; ch < 4; ch++) {
4440 tcal.init_cal[ch] = 0;
4441 tcal.tcomp_cal[ch] = 0;
4444 foreach_vch(ch) {
4445 tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
4446 tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
4459 foreach_vch(ch) {
4460 pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
4461 pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
4480 tcal.init_cal[ch] =
4481 (tcal.init_cal[ch] & 0xfffff000) |
4485 tcal.init_cal[ch] =