Lines Matching defs:ch
27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
28 ((n) << (8 + (ch) * 4)))
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
30 ((n) << (9 + (ch) * 4)))
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch)
138 rkclk_ddr_reset(ch, 1, 1);
140 rkclk_ddr_reset(ch, 1, 0);
142 rkclk_ddr_reset(ch, 0, 0);
146 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24,
156 static __pmusramfunc void select_per_cs_training_index(uint32_t ch,
160 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1)
161 set_cs_training_index(ch, rank);
164 static __pmusramfunc void override_write_leveling_value(uint32_t ch)
173 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16,
175 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)),
181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8);
184 static __pmusramfunc int data_training(uint32_t ch,
189 uint32_t rank = sdram_params->ch[ch].rank;
199 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22));
223 select_per_cs_training_index(ch, i);
225 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8);
228 mmio_clrsetbits_32(PI_REG(ch, 92),
233 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
239 obs_0 = mmio_read_32(PHY_REG(ch, 532));
240 obs_1 = mmio_read_32(PHY_REG(ch, 660));
241 obs_2 = mmio_read_32(PHY_REG(ch, 788));
256 mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
258 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8);
264 select_per_cs_training_index(ch, i);
266 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8);
268 mmio_clrsetbits_32(PI_REG(ch, 59),
274 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
281 obs_0 = mmio_read_32(PHY_REG(ch, 40));
282 obs_1 = mmio_read_32(PHY_REG(ch, 168));
283 obs_2 = mmio_read_32(PHY_REG(ch, 296));
284 obs_3 = mmio_read_32(PHY_REG(ch, 424));
301 mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
303 override_write_leveling_value(ch);
304 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8);
310 select_per_cs_training_index(ch, i);
312 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24,
318 mmio_clrsetbits_32(PI_REG(ch, 74),
324 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
331 obs_0 = mmio_read_32(PHY_REG(ch, 43));
332 obs_1 = mmio_read_32(PHY_REG(ch, 171));
333 obs_2 = mmio_read_32(PHY_REG(ch, 299));
334 obs_3 = mmio_read_32(PHY_REG(ch, 427));
350 mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
352 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24);
358 select_per_cs_training_index(ch, i);
360 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16,
363 mmio_clrsetbits_32(PI_REG(ch, 74),
368 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
383 mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
385 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16);
394 select_per_cs_training_index(ch, i);
399 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8);
401 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16,
404 mmio_clrsetbits_32(PI_REG(ch, 121),
409 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8;
418 mmio_write_32(PI_REG(ch, 175), 0x00003f7c);
420 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16);
424 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22));
434 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel];
438 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20));
439 if (ch->rank > 1)
440 cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row);
441 if (ch->row_3_4) {
458 struct rk3399_sdram_channel *info = &sdram_params->ch[i];
461 if (sdram_params->ch[i].col == 0)
475 if (sdram_params->ch[i].rank == 1)
489 static __pmusramfunc void pctl_cfg(uint32_t ch,
501 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1],
503 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]);
504 sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0],
507 sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896],
510 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT,
514 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24);
517 mmio_setbits_32(PI_REG(ch, 0), START);
518 mmio_setbits_32(CTL_REG(ch, 0), START);
522 tmp = mmio_read_32(PHY_REG(ch, 920));
523 tmp1 = mmio_read_32(PHY_REG(ch, 921));
524 tmp2 = mmio_read_32(PHY_REG(ch, 922));
531 if (mmio_read_32(PHY_REG(ch, 911)) & 0x1)
535 sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63);
538 sram_regcpy(PHY_REG(ch, 128 * i),
542 sram_regcpy(PHY_REG(ch, 512 + 128 * i),
549 uint32_t ch, ch_count;
565 for (ch = 0; ch < ch_count; ch++) {
571 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
576 if (data_training(ch, sdram_params, PI_FULL_TRAINING))
701 uint32_t ch, byte, i;
745 for (ch = 0; ch < sdram_params->num_channels; ch++) {
747 sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
748 mmio_read_32(PHY_REG(ch, 57 + byte * 128));
758 __pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq)
762 mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
763 mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
764 mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
765 mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
767 mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
768 mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
769 mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
772 mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
773 mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
774 mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
775 mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
777 mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
778 mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
779 mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
824 if (sdram_params->ch[channel].col)
845 sdram_params->ch[channel].ddrconfig);