xref: /arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1 /*
2  * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 
10 #include <mt_spm.h>
11 #include <mt_spm_cond.h>
12 #include <mt_spm_constraint.h>
13 #include <mt_spm_conservation.h>
14 #include <mt_spm_idle.h>
15 #include <mt_spm_internal.h>
16 #include <mt_spm_notifier.h>
17 #include <mt_spm_rc_internal.h>
18 #include <mt_spm_resource_req.h>
19 #include <mt_spm_reg.h>
20 #include <mt_spm_suspend.h>
21 #include <plat_pm.h>
22 
23 #define CONSTRAINT_CPU_BUCK_PCM_FLAG		\
24 	(SPM_FLAG_DISABLE_INFRA_PDN |		\
25 	 SPM_FLAG_DISABLE_VCORE_DVS |		\
26 	 SPM_FLAG_DISABLE_VCORE_DFS |		\
27 	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
28 	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
29 	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
30 
31 #define CONSTRAINT_CPU_BUCK_PCM_FLAG1		0U
32 
33 #define CONSTRAINT_CPU_BUCK_RESOURCE_REQ	\
34 	(MT_SPM_DRAM_S1 |			\
35 	 MT_SPM_DRAM_S0 |			\
36 	 MT_SPM_SYSPLL |			\
37 	 MT_SPM_INFRA |				\
38 	 MT_SPM_26M |				\
39 	 MT_SPM_XO_FPM)
40 
41 
42 static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
43 static unsigned int cpubuckldo_enter_cnt;
44 
45 static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
46 				     unsigned int *resource_req)
47 {
48 	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
49 	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
50 	*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
51 }
52 
53 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
54 {
55 	(void)cpu;
56 	(void)state_id;
57 
58 	return IS_MT_RM_RC_READY(cpubuckldo_status);
59 }
60 
61 unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
62 {
63 	(void)state_id;
64 
65 	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
66 }
67 
68 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
69 {
70 	(void)cpu;
71 
72 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
73 	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
74 			       (IS_PLAT_SUSPEND_ID(state_id) ?
75 				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
76 #endif
77 	if (IS_PLAT_SUSPEND_ID(state_id)) {
78 		mt_spm_suspend_enter(state_id,
79 				     MT_SPM_EX_OP_SET_SUSPEND_MODE |
80 				     MT_SPM_EX_OP_SET_WDT,
81 				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
82 	} else {
83 		mt_spm_idle_generic_enter(state_id, 0U,
84 					  spm_cpu_bcuk_ldo_conduct);
85 	}
86 
87 	cpubuckldo_enter_cnt++;
88 
89 	return 0;
90 }
91 
92 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
93 {
94 	(void)cpu;
95 
96 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
97 	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
98 #endif
99 	if (IS_PLAT_SUSPEND_ID(state_id)) {
100 		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
101 	} else {
102 		mt_spm_idle_generic_resume(state_id, 0U, NULL);
103 	}
104 
105 	return 0;
106 }
107