1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <drivers/delay_timer.h> 10 11 #include "mt_cpu_pm.h" 12 #include "mt_cpu_pm_cpc.h" 13 #include "mt_smp.h" 14 #include <mt_timer.h> 15 16 struct mtk_cpc_dev { 17 int auto_off; 18 unsigned int auto_thres_tick; 19 }; 20 21 static struct mtk_cpc_dev cpc; 22 23 static int mtk_cpc_last_core_prot(int prot_req, int resp_reg, int resp_ofs) 24 { 25 unsigned int staus; 26 unsigned int retry = 0; 27 28 while (retry < RETRY_CNT_MAX) { 29 retry++; 30 31 mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req); 32 33 udelay(1); 34 35 staus = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK; 36 37 if (staus == PROT_SUCCESS) { 38 return CPC_SUCCESS; 39 } else if (staus == PROT_GIVEUP) { 40 return CPC_ERR_FAIL; 41 } 42 } 43 44 return CPC_ERR_TIMEOUT; 45 } 46 47 static int mtk_cpu_pm_mcusys_prot_aquire(void) 48 { 49 return mtk_cpc_last_core_prot(MCUSYS_PROT_SET, CPC_MCUSYS_LAST_CORE_RESP, MCUSYS_RESP_OFS); 50 } 51 52 static void mtk_cpu_pm_mcusys_prot_release(void) 53 { 54 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); 55 } 56 57 int mtk_cpu_pm_cluster_prot_aquire(void) 58 { 59 return mtk_cpc_last_core_prot(CPUSYS_PROT_SET, CPC_MCUSYS_MP_LAST_CORE_RESP, 60 CPUSYS_RESP_OFS); 61 } 62 63 void mtk_cpu_pm_cluster_prot_release(void) 64 { 65 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); 66 } 67 68 static void mtk_cpc_cluster_cnt_backup(void) 69 { 70 /* single cluster */ 71 uint32_t backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP); 72 uint32_t curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER); 73 74 if ((curr_cnt & 0x7fff) == 0) { 75 curr_cnt = (curr_cnt >> 16) & 0x7fff; 76 } else { 77 curr_cnt = curr_cnt & 0x7fff; 78 } 79 80 mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt); 81 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); 82 } 83 84 static inline void mtk_cpc_mcusys_off_enable(bool enable) 85 { 86 mmio_write_32(CPC_MCUSYS_PWR_CTRL, enable ? 1 : 0); 87 } 88 89 void mtk_cpc_mcusys_off_reflect(void) 90 { 91 mtk_cpc_mcusys_off_enable(false); 92 mtk_cpu_pm_mcusys_prot_release(); 93 } 94 95 int mtk_cpc_mcusys_off_prepare(void) 96 { 97 if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) { 98 return CPC_ERR_FAIL; 99 } 100 101 mtk_cpc_cluster_cnt_backup(); 102 mtk_cpc_mcusys_off_enable(true); 103 104 return CPC_SUCCESS; 105 } 106 107 void mtk_cpc_core_on_hint_set(int cpu) 108 { 109 mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu)); 110 } 111 112 void mtk_cpc_core_on_hint_clr(int cpu) 113 { 114 mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu)); 115 } 116 117 static void mtk_cpc_dump_timestamp(void) 118 { 119 unsigned int id; 120 121 for (id = 0; id < CPC_TRACE_ID_NUM; id++) { 122 mmio_write_32(CPC_MCUSYS_TRACE_SEL, id); 123 124 memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id), 125 (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA, 126 CPC_TRACE_SIZE); 127 } 128 } 129 130 void mtk_cpc_time_sync(void) 131 { 132 uint64_t kt; 133 uint32_t systime_l, systime_h; 134 135 kt = sched_clock(); 136 systime_l = mmio_read_32(CNTSYS_L_REG); 137 systime_h = mmio_read_32(CNTSYS_H_REG); 138 139 /* sync kernel timer to cpc */ 140 mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt); 141 mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32)); 142 143 /* sync system timer to cpc */ 144 mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l); 145 mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h); 146 } 147 148 static void mtk_cpc_config(unsigned int cfg, unsigned int data) 149 { 150 switch (cfg) { 151 case CPC_SMC_CONFIG_PROF: 152 if (data) { 153 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); 154 } else { 155 mmio_clrbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); 156 } 157 break; 158 case CPC_SMC_CONFIG_AUTO_OFF: 159 if (data) { 160 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); 161 cpc.auto_off = 1; 162 } else { 163 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); 164 cpc.auto_off = 0; 165 } 166 break; 167 case CPC_SMC_CONFIG_AUTO_OFF_THRES: 168 cpc.auto_thres_tick = US_TO_TICKS(data); 169 mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick); 170 break; 171 case CPC_SMC_CONFIG_CNT_CLR: 172 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); 173 break; 174 case CPC_SMC_CONFIG_TIME_SYNC: 175 mtk_cpc_time_sync(); 176 break; 177 default: 178 break; 179 } 180 } 181 182 static unsigned int mtk_cpc_read_config(unsigned int cfg) 183 { 184 unsigned int res = 0; 185 186 switch (cfg) { 187 case CPC_SMC_CONFIG_PROF: 188 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? 1 : 0; 189 break; 190 case CPC_SMC_CONFIG_AUTO_OFF: 191 res = cpc.auto_off; 192 break; 193 case CPC_SMC_CONFIG_AUTO_OFF_THRES: 194 res = TICKS_TO_US(cpc.auto_thres_tick); 195 break; 196 case CPC_SMC_CONFIG_CNT_CLR: 197 default: 198 break; 199 } 200 201 return res; 202 } 203 204 uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2) 205 { 206 uint64_t res = 0; 207 208 switch (act) { 209 case CPC_SMC_EVENT_CPC_CONFIG: 210 mtk_cpc_config((unsigned int)arg1, (unsigned int)arg2); 211 break; 212 case CPC_SMC_EVENT_READ_CONFIG: 213 res = mtk_cpc_read_config((unsigned int)arg1); 214 break; 215 case CPC_SMC_EVENT_GIC_DPG_SET: 216 /* isolated_status = x2; */ 217 default: 218 break; 219 } 220 221 return res; 222 } 223 224 uint64_t mtk_cpc_trace_dump(uint64_t act, uint64_t arg1, uint64_t arg2) 225 { 226 switch (act) { 227 case CPC_SMC_EVENT_DUMP_TRACE_DATA: 228 mtk_cpc_dump_timestamp(); 229 break; 230 default: 231 break; 232 } 233 234 return 0; 235 } 236 237 void mtk_cpc_init(void) 238 { 239 #if CONFIG_MTK_SMP_EN 240 mt_smp_init(); 241 #endif 242 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, (CPC_DBG_EN | CPC_CALC_EN)); 243 244 cpc.auto_off = 1; 245 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, (CPC_OFF_PRE_EN | 246 ((cpc.auto_off > 0) ? CPC_AUTO_OFF_EN : 0))); 247 248 mtk_cpc_config(CPC_SMC_CONFIG_AUTO_OFF_THRES, 8000); 249 250 /* enable CPC */ 251 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); 252 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN); 253 } 254