1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <drivers/delay_timer.h> 9 #include <lib/mmio.h> 10 11 #include <armada_common.h> 12 13 /* 14 * If bootrom is currently at BLE there's no need to include the memory 15 * maps structure at this point 16 */ 17 #include <mvebu_def.h> 18 #ifndef IMAGE_BLE 19 20 /***************************************************************************** 21 * GPIO Configuration 22 ***************************************************************************** 23 */ 24 #define MPP_CONTROL_REGISTER 0xf2440018 25 #define MPP_CONTROL_MPP_SEL_52_MASK 0xf0000 26 #define GPIO_DATA_OUT1_REGISTER 0xf2440140 27 #define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144 28 #define GPIO52_MASK 0x100000 29 30 /* Reset PCIe via GPIO number 52 */ 31 int marvell_gpio_config(void) 32 { 33 uint32_t reg; 34 35 reg = mmio_read_32(MPP_CONTROL_REGISTER); 36 reg |= MPP_CONTROL_MPP_SEL_52_MASK; 37 mmio_write_32(MPP_CONTROL_REGISTER, reg); 38 39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); 40 reg |= GPIO52_MASK; 41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); 42 43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); 44 reg &= ~GPIO52_MASK; 45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); 46 udelay(100); 47 48 return 0; 49 } 50 51 /***************************************************************************** 52 * AMB Configuration 53 ***************************************************************************** 54 */ 55 struct addr_map_win amb_memory_map[] = { 56 /* CP1 SPI1 CS0 Direct Mode access */ 57 {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, 58 }; 59 60 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, 61 uintptr_t base) 62 { 63 *win = amb_memory_map; 64 if (*win == NULL) 65 *size = 0; 66 else 67 *size = ARRAY_SIZE(amb_memory_map); 68 69 return 0; 70 } 71 #endif 72 73 /***************************************************************************** 74 * IO WIN Configuration 75 ***************************************************************************** 76 */ 77 struct addr_map_win io_win_memory_map[] = { 78 /* CP1 (MCI0) internal regs */ 79 {0x00000000f4000000, 0x2000000, MCI_0_TID}, 80 #ifndef IMAGE_BLE 81 /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/ 82 {0x00000000f9000000, 0x2000000, MCI_0_TID}, 83 /* PCIe1 on CP1*/ 84 {0x00000000fb000000, 0x1000000, MCI_0_TID}, 85 /* PCIe2 on CP1*/ 86 {0x00000000fc000000, 0x1000000, MCI_0_TID}, 87 /* MCI 0 indirect window */ 88 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, 89 /* MCI 1 indirect window */ 90 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, 91 #endif 92 }; 93 94 uint32_t marvell_get_io_win_gcr_target(int ap_index) 95 { 96 return PIDI_TID; 97 } 98 99 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, 100 uint32_t *size) 101 { 102 *win = io_win_memory_map; 103 if (*win == NULL) 104 *size = 0; 105 else 106 *size = ARRAY_SIZE(io_win_memory_map); 107 108 return 0; 109 } 110 111 #ifndef IMAGE_BLE 112 /***************************************************************************** 113 * IOB Configuration 114 ***************************************************************************** 115 */ 116 struct addr_map_win iob_memory_map_cp0[] = { 117 /* CP0 */ 118 /* PEX1_X1 window */ 119 {0x00000000f7000000, 0x1000000, PEX1_TID}, 120 /* PEX2_X1 window */ 121 {0x00000000f8000000, 0x1000000, PEX2_TID}, 122 /* PEX0_X4 window */ 123 {0x00000000f6000000, 0x1000000, PEX0_TID}, 124 {0x00000000c0000000, 0x30000000, PEX0_TID}, 125 {0x0000000800000000, 0x100000000, PEX0_TID}, 126 }; 127 128 struct addr_map_win iob_memory_map_cp1[] = { 129 /* CP1 */ 130 /* SPI1_CS0 (RUNIT) window */ 131 {0x00000000f9000000, 0x1000000, RUNIT_TID}, 132 /* PEX1_X1 window */ 133 {0x00000000fb000000, 0x1000000, PEX1_TID}, 134 /* PEX2_X1 window */ 135 {0x00000000fc000000, 0x1000000, PEX2_TID}, 136 /* PEX0_X4 window */ 137 {0x00000000fa000000, 0x1000000, PEX0_TID} 138 }; 139 140 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, 141 uintptr_t base) 142 { 143 switch (base) { 144 case MVEBU_CP_REGS_BASE(0): 145 *win = iob_memory_map_cp0; 146 *size = ARRAY_SIZE(iob_memory_map_cp0); 147 return 0; 148 case MVEBU_CP_REGS_BASE(1): 149 *win = iob_memory_map_cp1; 150 *size = ARRAY_SIZE(iob_memory_map_cp1); 151 return 0; 152 default: 153 *size = 0; 154 *win = 0; 155 return 1; 156 } 157 } 158 #endif 159 160 /***************************************************************************** 161 * CCU Configuration 162 ***************************************************************************** 163 */ 164 struct addr_map_win ccu_memory_map[] = { 165 #ifdef IMAGE_BLE 166 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ 167 #else 168 #if LLC_SRAM 169 {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID}, 170 #endif 171 {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ 172 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ 173 {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ 174 #endif 175 }; 176 177 uint32_t marvell_get_ccu_gcr_target(int ap) 178 { 179 return DRAM_0_TID; 180 } 181 182 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, 183 uint32_t *size) 184 { 185 *win = ccu_memory_map; 186 *size = ARRAY_SIZE(ccu_memory_map); 187 188 return 0; 189 } 190 191 /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */ 192 193 /***************************************************************************** 194 * SKIP IMAGE Configuration 195 ***************************************************************************** 196 */ 197 void *plat_marvell_get_skip_image_data(void) 198 { 199 /* No recovery button on A8k-MCBIN board */ 200 return NULL; 201 } 202