| /arm-trusted-firmware/plat/mediatek/drivers/emi_mpu/mt8188/ |
| H A D | emi_mpu_priv.h | 21 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
23 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
34 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
36 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
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| /arm-trusted-firmware/plat/mediatek/drivers/apusys/devapc/ |
| H A D | apusys_dapc_v1.h | 110 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \ argument
117 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain) \ argument
124 #define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain) \ argument
131 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain) \ argument
138 #define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain) \ argument
145 SLAVE_FORBID_EXCEPT_D5_D7_NO_PROTECT(domain) global() argument
152 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT(domain) global() argument
[all...] |
| /arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/ |
| H A D | apupwr_clkctl.c | 115 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain) in apupwr_smc_acc_set_parent() argument
200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate() argument
[all...] |
| H A D | apupll.c | 90 static int32_t vd2pllidx(enum dvfs_voltage_domain domain) in vd2pllidx() argument
507 anpu_pll_set_rate(enum dvfs_voltage_domain domain,enum pll_set_rate_mode mode,int32_t freq) anpu_pll_set_rate() argument
[all...] |
| /arm-trusted-firmware/plat/mediatek/mt8186/drivers/emi_mpu/ |
| H A D | emi_mpu.h | 23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
|
| /arm-trusted-firmware/plat/mediatek/mt8195/drivers/emi_mpu/ |
| H A D | emi_mpu.h | 23 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) argument
25 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) argument
38 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) argument
40 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) argument
|
| /arm-trusted-firmware/plat/mediatek/mt8192/drivers/emi_mpu/ |
| H A D | emi_mpu.h | 51 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4) argument
53 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4) argument
|
| /arm-trusted-firmware/plat/mediatek/mt8183/drivers/devapc/ |
| H A D | devapc.c | 32 static void set_master_domain(uint32_t master_index, enum MASK_DOM domain) in set_master_domain() argument
|
| /arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| H A D | mt_cpu_pm.c | 337 static unsigned int cpupm_get_pstate(enum mt_cpupm_pwr_domain domain, in cpupm_get_pstate() argument
|
| /arm-trusted-firmware/plat/mediatek/lib/pm/armv8_2/ |
| H A D | pwr_ctrl.c | 80 static unsigned int get_mediatek_pstate(unsigned int domain, unsigned int psci_state, in get_mediatek_pstate() argument
[all...] |
| /arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ |
| H A D | ti_sci_protocol.h | 124 uint8_t domain; member
|