1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef EMI_MPU_PRIV_H 8*91f16700Schasinglulu #define EMI_MPU_PRIV_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define ENABLE_EMI_MPU_SW_LOCK (1) 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000) 13*91f16700Schasinglulu #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004) 14*91f16700Schasinglulu #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) 15*91f16700Schasinglulu #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) 16*91f16700Schasinglulu #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4)) 17*91f16700Schasinglulu #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4)) 18*91f16700Schasinglulu #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) 19*91f16700Schasinglulu #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 20*91f16700Schasinglulu #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) 21*91f16700Schasinglulu #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) 22*91f16700Schasinglulu #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) 23*91f16700Schasinglulu #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000) 26*91f16700Schasinglulu #define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004) 27*91f16700Schasinglulu #define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100) 28*91f16700Schasinglulu #define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200) 29*91f16700Schasinglulu #define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4)) 30*91f16700Schasinglulu #define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4)) 31*91f16700Schasinglulu #define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300) 32*91f16700Schasinglulu #define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 33*91f16700Schasinglulu #define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800) 34*91f16700Schasinglulu #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) 35*91f16700Schasinglulu #define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900) 36*91f16700Schasinglulu #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define EMI_MPU_DOMAIN_NUM (16) 39*91f16700Schasinglulu #define EMI_MPU_REGION_NUM (32) 40*91f16700Schasinglulu #define EMI_MPU_ALIGN_BITS (16) 41*91f16700Schasinglulu #define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* APU EMI MPU Setting */ 46*91f16700Schasinglulu #define APUSYS_SEC_BUF_EMI_REGION (21) 47*91f16700Schasinglulu #define APUSYS_SEC_BUF_PA (0x55000000) 48*91f16700Schasinglulu #define APUSYS_SEC_BUF_SZ (0x100000) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #endif 51