1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <pdef_tbb_cert.h> 8*91f16700Schasinglulu #include <pdef_tbb_ext.h> 9*91f16700Schasinglulu #include <pdef_tbb_key.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu static cert_t pdef_tbb_certs[] = { 12*91f16700Schasinglulu [DDR_FW_KEY_CERT - DDR_FW_KEY_CERT] = { 13*91f16700Schasinglulu .id = DDR_FW_KEY_CERT, 14*91f16700Schasinglulu .opt = "ddr-fw-key-cert", 15*91f16700Schasinglulu .help_msg = "DDR Firmware Key Certificate (output file)", 16*91f16700Schasinglulu .fn = NULL, 17*91f16700Schasinglulu .cn = "DDR Firmware Key Certificate", 18*91f16700Schasinglulu .key = TRUSTED_WORLD_KEY, 19*91f16700Schasinglulu .issuer = DDR_FW_KEY_CERT, 20*91f16700Schasinglulu .ext = { 21*91f16700Schasinglulu TRUSTED_FW_NVCOUNTER_EXT, 22*91f16700Schasinglulu DDR_FW_CONTENT_CERT_PK_EXT, 23*91f16700Schasinglulu }, 24*91f16700Schasinglulu .num_ext = 2 25*91f16700Schasinglulu }, 26*91f16700Schasinglulu [DDR_UDIMM_FW_CONTENT_CERT - DDR_FW_KEY_CERT] = { 27*91f16700Schasinglulu .id = DDR_UDIMM_FW_CONTENT_CERT, 28*91f16700Schasinglulu .opt = "ddr-udimm-fw-cert", 29*91f16700Schasinglulu .help_msg = "DDR UDIMM Firmware Content Certificate (output file)", 30*91f16700Schasinglulu .fn = NULL, 31*91f16700Schasinglulu .cn = "DDR UDIMM Firmware Content Certificate", 32*91f16700Schasinglulu .key = DDR_FW_CONTENT_KEY, 33*91f16700Schasinglulu .issuer = DDR_UDIMM_FW_CONTENT_CERT, 34*91f16700Schasinglulu .ext = { 35*91f16700Schasinglulu TRUSTED_FW_NVCOUNTER_EXT, 36*91f16700Schasinglulu DDR_IMEM_UDIMM_1D_HASH_EXT, 37*91f16700Schasinglulu DDR_IMEM_UDIMM_2D_HASH_EXT, 38*91f16700Schasinglulu DDR_DMEM_UDIMM_1D_HASH_EXT, 39*91f16700Schasinglulu DDR_DMEM_UDIMM_2D_HASH_EXT, 40*91f16700Schasinglulu }, 41*91f16700Schasinglulu .num_ext = 5 42*91f16700Schasinglulu }, 43*91f16700Schasinglulu [DDR_RDIMM_FW_CONTENT_CERT - DDR_FW_KEY_CERT] = { 44*91f16700Schasinglulu .id = DDR_RDIMM_FW_CONTENT_CERT, 45*91f16700Schasinglulu .opt = "ddr-rdimm-fw-cert", 46*91f16700Schasinglulu .help_msg = "DDR RDIMM Firmware Content Certificate (output file)", 47*91f16700Schasinglulu .fn = NULL, 48*91f16700Schasinglulu .cn = "DDR RDIMM Firmware Content Certificate", 49*91f16700Schasinglulu .key = DDR_FW_CONTENT_KEY, 50*91f16700Schasinglulu .issuer = DDR_RDIMM_FW_CONTENT_CERT, 51*91f16700Schasinglulu .ext = { 52*91f16700Schasinglulu TRUSTED_FW_NVCOUNTER_EXT, 53*91f16700Schasinglulu DDR_IMEM_RDIMM_1D_HASH_EXT, 54*91f16700Schasinglulu DDR_IMEM_RDIMM_2D_HASH_EXT, 55*91f16700Schasinglulu DDR_DMEM_RDIMM_1D_HASH_EXT, 56*91f16700Schasinglulu DDR_DMEM_RDIMM_2D_HASH_EXT, 57*91f16700Schasinglulu }, 58*91f16700Schasinglulu .num_ext = 5 59*91f16700Schasinglulu } 60*91f16700Schasinglulu }; 61*91f16700Schasinglulu 62*91f16700Schasinglulu PLAT_REGISTER_COT(pdef_tbb_certs); 63