1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <context.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu/* ----------------------------------------------------------------------------- 13*91f16700Schasinglulu * Very simple stackless exception handlers used by the spm shim layer. 14*91f16700Schasinglulu * ----------------------------------------------------------------------------- 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu .globl spm_shim_exceptions_ptr 17*91f16700Schasinglulu 18*91f16700Schasingluluvector_base spm_shim_exceptions_ptr, .spm_shim_exceptions 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* ----------------------------------------------------- 21*91f16700Schasinglulu * Current EL with SP0 : 0x0 - 0x200 22*91f16700Schasinglulu * ----------------------------------------------------- 23*91f16700Schasinglulu */ 24*91f16700Schasingluluvector_entry SynchronousExceptionSP0, .spm_shim_exceptions 25*91f16700Schasinglulu b . 26*91f16700Schasingluluend_vector_entry SynchronousExceptionSP0 27*91f16700Schasinglulu 28*91f16700Schasingluluvector_entry IrqSP0, .spm_shim_exceptions 29*91f16700Schasinglulu b . 30*91f16700Schasingluluend_vector_entry IrqSP0 31*91f16700Schasinglulu 32*91f16700Schasingluluvector_entry FiqSP0, .spm_shim_exceptions 33*91f16700Schasinglulu b . 34*91f16700Schasingluluend_vector_entry FiqSP0 35*91f16700Schasinglulu 36*91f16700Schasingluluvector_entry SErrorSP0, .spm_shim_exceptions 37*91f16700Schasinglulu b . 38*91f16700Schasingluluend_vector_entry SErrorSP0 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* ----------------------------------------------------- 41*91f16700Schasinglulu * Current EL with SPx: 0x200 - 0x400 42*91f16700Schasinglulu * ----------------------------------------------------- 43*91f16700Schasinglulu */ 44*91f16700Schasingluluvector_entry SynchronousExceptionSPx, .spm_shim_exceptions 45*91f16700Schasinglulu b . 46*91f16700Schasingluluend_vector_entry SynchronousExceptionSPx 47*91f16700Schasinglulu 48*91f16700Schasingluluvector_entry IrqSPx, .spm_shim_exceptions 49*91f16700Schasinglulu b . 50*91f16700Schasingluluend_vector_entry IrqSPx 51*91f16700Schasinglulu 52*91f16700Schasingluluvector_entry FiqSPx, .spm_shim_exceptions 53*91f16700Schasinglulu b . 54*91f16700Schasingluluend_vector_entry FiqSPx 55*91f16700Schasinglulu 56*91f16700Schasingluluvector_entry SErrorSPx, .spm_shim_exceptions 57*91f16700Schasinglulu b . 58*91f16700Schasingluluend_vector_entry SErrorSPx 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* ----------------------------------------------------- 61*91f16700Schasinglulu * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 62*91f16700Schasinglulu * are handled since secure_partition does not implement 63*91f16700Schasinglulu * a lower EL 64*91f16700Schasinglulu * ----------------------------------------------------- 65*91f16700Schasinglulu */ 66*91f16700Schasingluluvector_entry SynchronousExceptionA64, .spm_shim_exceptions 67*91f16700Schasinglulu msr tpidr_el1, x30 68*91f16700Schasinglulu mrs x30, esr_el1 69*91f16700Schasinglulu ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 70*91f16700Schasinglulu 71*91f16700Schasinglulu cmp x30, #EC_AARCH64_SVC 72*91f16700Schasinglulu b.eq do_smc 73*91f16700Schasinglulu 74*91f16700Schasinglulu cmp x30, #EC_AARCH32_SVC 75*91f16700Schasinglulu b.eq do_smc 76*91f16700Schasinglulu 77*91f16700Schasinglulu cmp x30, #EC_AARCH64_SYS 78*91f16700Schasinglulu b.eq handle_sys_trap 79*91f16700Schasinglulu 80*91f16700Schasinglulu /* Fail in all the other cases */ 81*91f16700Schasinglulu b panic 82*91f16700Schasinglulu 83*91f16700Schasinglulu /* --------------------------------------------- 84*91f16700Schasinglulu * Tell SPM that we are done initialising 85*91f16700Schasinglulu * --------------------------------------------- 86*91f16700Schasinglulu */ 87*91f16700Schasingluludo_smc: 88*91f16700Schasinglulu mrs x30, tpidr_el1 89*91f16700Schasinglulu smc #0 90*91f16700Schasinglulu exception_return 91*91f16700Schasinglulu 92*91f16700Schasinglulu /* AArch64 system instructions trap are handled as a panic for now */ 93*91f16700Schasingluluhandle_sys_trap: 94*91f16700Schasinglulupanic: 95*91f16700Schasinglulu b panic 96*91f16700Schasingluluend_vector_entry SynchronousExceptionA64 97*91f16700Schasinglulu 98*91f16700Schasingluluvector_entry IrqA64, .spm_shim_exceptions 99*91f16700Schasinglulu b . 100*91f16700Schasingluluend_vector_entry IrqA64 101*91f16700Schasinglulu 102*91f16700Schasingluluvector_entry FiqA64, .spm_shim_exceptions 103*91f16700Schasinglulu b . 104*91f16700Schasingluluend_vector_entry FiqA64 105*91f16700Schasinglulu 106*91f16700Schasingluluvector_entry SErrorA64, .spm_shim_exceptions 107*91f16700Schasinglulu b . 108*91f16700Schasingluluend_vector_entry SErrorA64 109*91f16700Schasinglulu 110*91f16700Schasinglulu /* ----------------------------------------------------- 111*91f16700Schasinglulu * Lower EL using AArch32 : 0x600 - 0x800 112*91f16700Schasinglulu * ----------------------------------------------------- 113*91f16700Schasinglulu */ 114*91f16700Schasingluluvector_entry SynchronousExceptionA32, .spm_shim_exceptions 115*91f16700Schasinglulu b . 116*91f16700Schasingluluend_vector_entry SynchronousExceptionA32 117*91f16700Schasinglulu 118*91f16700Schasingluluvector_entry IrqA32, .spm_shim_exceptions 119*91f16700Schasinglulu b . 120*91f16700Schasingluluend_vector_entry IrqA32 121*91f16700Schasinglulu 122*91f16700Schasingluluvector_entry FiqA32, .spm_shim_exceptions 123*91f16700Schasinglulu b . 124*91f16700Schasingluluend_vector_entry FiqA32 125*91f16700Schasinglulu 126*91f16700Schasingluluvector_entry SErrorA32, .spm_shim_exceptions 127*91f16700Schasinglulu b . 128*91f16700Schasingluluend_vector_entry SErrorA32 129