1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef ERRATA_CPUSPEC_H 8*91f16700Schasinglulu #define ERRATA_CPUSPEC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu #include <arch_helpers.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #if __aarch64__ 14*91f16700Schasinglulu #include <cortex_a35.h> 15*91f16700Schasinglulu #include <cortex_a510.h> 16*91f16700Schasinglulu #include <cortex_a53.h> 17*91f16700Schasinglulu #include <cortex_a57.h> 18*91f16700Schasinglulu #include <cortex_a55.h> 19*91f16700Schasinglulu #include <cortex_a710.h> 20*91f16700Schasinglulu #include <cortex_a72.h> 21*91f16700Schasinglulu #include <cortex_a73.h> 22*91f16700Schasinglulu #include <cortex_a75.h> 23*91f16700Schasinglulu #include <cortex_a76.h> 24*91f16700Schasinglulu #include <cortex_a77.h> 25*91f16700Schasinglulu #include <cortex_a78.h> 26*91f16700Schasinglulu #include <cortex_a78_ae.h> 27*91f16700Schasinglulu #include <cortex_a78c.h> 28*91f16700Schasinglulu #include <cortex_a715.h> 29*91f16700Schasinglulu #include <cortex_x1.h> 30*91f16700Schasinglulu #include <cortex_x2.h> 31*91f16700Schasinglulu #include <cortex_x3.h> 32*91f16700Schasinglulu #include <neoverse_n1.h> 33*91f16700Schasinglulu #include <neoverse_n2.h> 34*91f16700Schasinglulu #include <neoverse_v1.h> 35*91f16700Schasinglulu #include <neoverse_v2.h> 36*91f16700Schasinglulu #else 37*91f16700Schasinglulu #include <cortex_a15.h> 38*91f16700Schasinglulu #include <cortex_a17.h> 39*91f16700Schasinglulu #include <cortex_a57.h> 40*91f16700Schasinglulu #include <cortex_a9.h> 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define MAX_ERRATA_ENTRIES 32 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1) 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* Default values for unused memory in the array */ 48*91f16700Schasinglulu #define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false, false} 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 51*91f16700Schasinglulu 52*91f16700Schasinglulu #define RXPX_RANGE(x, y, z) (((x >= y) && (x <= z)) ? true : false) 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* 55*91f16700Schasinglulu * CPU specific values for errata handling 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu struct em_cpu{ 58*91f16700Schasinglulu unsigned int em_errata_id; 59*91f16700Schasinglulu unsigned char em_rxpx_lo; /* lowest revision of errata applicable for the cpu */ 60*91f16700Schasinglulu unsigned char em_rxpx_hi; /* highest revision of errata applicable for the cpu */ 61*91f16700Schasinglulu bool errata_enabled; /* indicate if errata enabled */ 62*91f16700Schasinglulu /* flag to indicate if errata query is based out of non-arm interconnect */ 63*91f16700Schasinglulu bool non_arm_interconnect; 64*91f16700Schasinglulu }; 65*91f16700Schasinglulu 66*91f16700Schasinglulu struct em_cpu_list{ 67*91f16700Schasinglulu /* field to hold cpu specific part number defined in midr reg */ 68*91f16700Schasinglulu unsigned long cpu_partnumber; 69*91f16700Schasinglulu struct em_cpu cpu_errata_list[MAX_ERRATA_ENTRIES]; 70*91f16700Schasinglulu }; 71*91f16700Schasinglulu 72*91f16700Schasinglulu int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag); 73*91f16700Schasinglulu #endif /* ERRATA_CPUSPEC_H */ 74