1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef TLKD_PRIVATE_H 8*91f16700Schasinglulu #define TLKD_PRIVATE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <arch.h> 13*91f16700Schasinglulu #include <bl31/interrupt_mgmt.h> 14*91f16700Schasinglulu #include <context.h> 15*91f16700Schasinglulu #include <lib/psci/psci.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* 18*91f16700Schasinglulu * This flag is used by the TLKD to determine if the SP is servicing a yielding 19*91f16700Schasinglulu * SMC request prior to programming the next entry into the SP e.g. if SP 20*91f16700Schasinglulu * execution is preempted by a non-secure interrupt and handed control to the 21*91f16700Schasinglulu * normal world. If another request which is distinct from what the SP was 22*91f16700Schasinglulu * previously doing arrives, then this flag will be help the TLKD to either 23*91f16700Schasinglulu * reject the new request or service it while ensuring that the previous context 24*91f16700Schasinglulu * is not corrupted. 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu #define YIELD_SMC_ACTIVE_FLAG_SHIFT 2 27*91f16700Schasinglulu #define YIELD_SMC_ACTIVE_FLAG_MASK 1 28*91f16700Schasinglulu #define get_yield_smc_active_flag(state) \ 29*91f16700Schasinglulu (((state) >> YIELD_SMC_ACTIVE_FLAG_SHIFT) \ 30*91f16700Schasinglulu & YIELD_SMC_ACTIVE_FLAG_MASK) 31*91f16700Schasinglulu #define set_yield_smc_active_flag(state) ((state) |= \ 32*91f16700Schasinglulu (1 << YIELD_SMC_ACTIVE_FLAG_SHIFT)) 33*91f16700Schasinglulu #define clr_yield_smc_active_flag(state) ((state) &= \ 34*91f16700Schasinglulu ~(YIELD_SMC_ACTIVE_FLAG_MASK \ 35*91f16700Schasinglulu << YIELD_SMC_ACTIVE_FLAG_SHIFT)) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * Translate virtual address received from the NS world 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu #define TLK_TRANSLATE_NS_VADDR 4 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * Secure Payload execution state information i.e. aarch32 or aarch64 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu #define SP_AARCH32 MODE_RW_32 46*91f16700Schasinglulu #define SP_AARCH64 MODE_RW_64 47*91f16700Schasinglulu 48*91f16700Schasinglulu /******************************************************************************* 49*91f16700Schasinglulu * Number of cpus that the present on this platform. TODO: Rely on a topology 50*91f16700Schasinglulu * tree to determine this in the future to avoid assumptions about mpidr 51*91f16700Schasinglulu * allocation 52*91f16700Schasinglulu ******************************************************************************/ 53*91f16700Schasinglulu #define TLKD_CORE_COUNT PLATFORM_CORE_COUNT 54*91f16700Schasinglulu 55*91f16700Schasinglulu /******************************************************************************* 56*91f16700Schasinglulu * Constants that allow assembler code to preserve callee-saved registers of the 57*91f16700Schasinglulu * C runtime context while performing a security state switch. 58*91f16700Schasinglulu ******************************************************************************/ 59*91f16700Schasinglulu #define TLKD_C_RT_CTX_X19 0x0 60*91f16700Schasinglulu #define TLKD_C_RT_CTX_X20 0x8 61*91f16700Schasinglulu #define TLKD_C_RT_CTX_X21 0x10 62*91f16700Schasinglulu #define TLKD_C_RT_CTX_X22 0x18 63*91f16700Schasinglulu #define TLKD_C_RT_CTX_X23 0x20 64*91f16700Schasinglulu #define TLKD_C_RT_CTX_X24 0x28 65*91f16700Schasinglulu #define TLKD_C_RT_CTX_X25 0x30 66*91f16700Schasinglulu #define TLKD_C_RT_CTX_X26 0x38 67*91f16700Schasinglulu #define TLKD_C_RT_CTX_X27 0x40 68*91f16700Schasinglulu #define TLKD_C_RT_CTX_X28 0x48 69*91f16700Schasinglulu #define TLKD_C_RT_CTX_X29 0x50 70*91f16700Schasinglulu #define TLKD_C_RT_CTX_X30 0x58 71*91f16700Schasinglulu #define TLKD_C_RT_CTX_SIZE 0x60 72*91f16700Schasinglulu #define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) 73*91f16700Schasinglulu 74*91f16700Schasinglulu #ifndef __ASSEMBLER__ 75*91f16700Schasinglulu 76*91f16700Schasinglulu #include <stdint.h> 77*91f16700Schasinglulu 78*91f16700Schasinglulu #include <lib/cassert.h> 79*91f16700Schasinglulu 80*91f16700Schasinglulu /* AArch64 callee saved general purpose register context structure. */ 81*91f16700Schasinglulu DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES); 82*91f16700Schasinglulu 83*91f16700Schasinglulu /* 84*91f16700Schasinglulu * Compile time assertion to ensure that both the compiler and linker 85*91f16700Schasinglulu * have the same double word aligned view of the size of the C runtime 86*91f16700Schasinglulu * register context. 87*91f16700Schasinglulu */ 88*91f16700Schasinglulu CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), 89*91f16700Schasinglulu assert_tlkd_c_rt_regs_size_mismatch); 90*91f16700Schasinglulu 91*91f16700Schasinglulu /******************************************************************************* 92*91f16700Schasinglulu * Structure which helps the SPD to maintain the per-cpu state of the SP. 93*91f16700Schasinglulu * 'state' - collection of flags to track SP state e.g. on/off 94*91f16700Schasinglulu * 'mpidr' - mpidr to associate a context with a cpu 95*91f16700Schasinglulu * 'c_rt_ctx' - stack address to restore C runtime context from after 96*91f16700Schasinglulu * returning from a synchronous entry into the SP. 97*91f16700Schasinglulu * 'cpu_ctx' - space to maintain SP architectural state 98*91f16700Schasinglulu * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 99*91f16700Schasinglulu * which will queried using the TSP_GET_ARGS SMC by TSP. 100*91f16700Schasinglulu ******************************************************************************/ 101*91f16700Schasinglulu typedef struct tlk_context { 102*91f16700Schasinglulu uint32_t state; 103*91f16700Schasinglulu uint64_t mpidr; 104*91f16700Schasinglulu uint64_t c_rt_ctx; 105*91f16700Schasinglulu cpu_context_t cpu_ctx; 106*91f16700Schasinglulu } tlk_context_t; 107*91f16700Schasinglulu 108*91f16700Schasinglulu /******************************************************************************* 109*91f16700Schasinglulu * Function & Data prototypes 110*91f16700Schasinglulu ******************************************************************************/ 111*91f16700Schasinglulu uint64_t tlkd_va_translate(uintptr_t va, int type); 112*91f16700Schasinglulu uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx); 113*91f16700Schasinglulu void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 114*91f16700Schasinglulu uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx); 115*91f16700Schasinglulu void __dead2 tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, 116*91f16700Schasinglulu uint64_t ret); 117*91f16700Schasinglulu void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, 118*91f16700Schasinglulu uint32_t rw, 119*91f16700Schasinglulu uint64_t pc, 120*91f16700Schasinglulu tlk_context_t *tlk_ctx); 121*91f16700Schasinglulu 122*91f16700Schasinglulu #endif /*__ASSEMBLER__*/ 123*91f16700Schasinglulu 124*91f16700Schasinglulu #endif /* TLKD_PRIVATE_H */ 125