1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef __PNCD_PRIVATE_H__ 9*91f16700Schasinglulu #define __PNCD_PRIVATE_H__ 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifndef __ASSEMBLER__ 12*91f16700Schasinglulu #include <stdint.h> 13*91f16700Schasinglulu #endif /* __ASSEMBLER __ */ 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <context.h> 16*91f16700Schasinglulu #ifndef __ASSEMBLER__ 17*91f16700Schasinglulu #include <lib/cassert.h> 18*91f16700Schasinglulu #endif /* __ASSEMBLER __ */ 19*91f16700Schasinglulu 20*91f16700Schasinglulu #include <platform_def.h> 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * Constants that allow assembler code to preserve callee-saved registers of the 24*91f16700Schasinglulu * C runtime context while performing a security state switch. 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define PNCD_C_RT_CTX_X19 U(0x0) 27*91f16700Schasinglulu #define PNCD_C_RT_CTX_X20 U(0x8) 28*91f16700Schasinglulu #define PNCD_C_RT_CTX_X21 U(0x10) 29*91f16700Schasinglulu #define PNCD_C_RT_CTX_X22 U(0x18) 30*91f16700Schasinglulu #define PNCD_C_RT_CTX_X23 U(0x20) 31*91f16700Schasinglulu #define PNCD_C_RT_CTX_X24 U(0x28) 32*91f16700Schasinglulu #define PNCD_C_RT_CTX_X25 U(0x30) 33*91f16700Schasinglulu #define PNCD_C_RT_CTX_X26 U(0x38) 34*91f16700Schasinglulu #define PNCD_C_RT_CTX_X27 U(0x40) 35*91f16700Schasinglulu #define PNCD_C_RT_CTX_X28 U(0x48) 36*91f16700Schasinglulu #define PNCD_C_RT_CTX_X29 U(0x50) 37*91f16700Schasinglulu #define PNCD_C_RT_CTX_X30 U(0x58) 38*91f16700Schasinglulu #define PNCD_C_RT_CTX_SIZE U(0x60) 39*91f16700Schasinglulu #define PNCD_C_RT_CTX_ENTRIES (PNCD_C_RT_CTX_SIZE >> DWORD_SHIFT) 40*91f16700Schasinglulu 41*91f16700Schasinglulu #ifndef __ASSEMBLER__ 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* AArch64 callee saved general purpose register context structure. */ 44*91f16700Schasinglulu DEFINE_REG_STRUCT(c_rt_regs, PNCD_C_RT_CTX_ENTRIES); 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* 47*91f16700Schasinglulu * Compile time assertion to ensure that both the compiler and linker 48*91f16700Schasinglulu * have the same double word aligned view of the size of the C runtime 49*91f16700Schasinglulu * register context. 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu CASSERT(sizeof(c_rt_regs_t) == PNCD_C_RT_CTX_SIZE, 52*91f16700Schasinglulu assert_spd_c_rt_regs_size_mismatch); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /******************************************************************************* 55*91f16700Schasinglulu * Structure which helps the SPD to maintain the per-cpu state of the SP. 56*91f16700Schasinglulu * 'mpidr' - mpidr of the CPU running PNC 57*91f16700Schasinglulu * 'c_rt_ctx' - stack address to restore C runtime context from after 58*91f16700Schasinglulu * returning from a synchronous entry into the SP. 59*91f16700Schasinglulu * 'cpu_ctx' - space to maintain SP architectural state 60*91f16700Schasinglulu ******************************************************************************/ 61*91f16700Schasinglulu typedef struct pnc_context { 62*91f16700Schasinglulu uint64_t mpidr; 63*91f16700Schasinglulu uint64_t c_rt_ctx; 64*91f16700Schasinglulu cpu_context_t cpu_ctx; 65*91f16700Schasinglulu } pnc_context_t; 66*91f16700Schasinglulu 67*91f16700Schasinglulu /******************************************************************************* 68*91f16700Schasinglulu * Function & Data prototypes 69*91f16700Schasinglulu ******************************************************************************/ 70*91f16700Schasinglulu uint64_t pncd_enter_sp(uint64_t *c_rt_ctx); 71*91f16700Schasinglulu void __dead2 pncd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 72*91f16700Schasinglulu uint64_t pncd_synchronous_sp_entry(pnc_context_t *pnc_ctx); 73*91f16700Schasinglulu void __dead2 pncd_synchronous_sp_exit(pnc_context_t *pnc_ctx, uint64_t ret); 74*91f16700Schasinglulu void pncd_init_pnc_ep_state(struct entry_point_info *pnc_ep, 75*91f16700Schasinglulu uint64_t pc, 76*91f16700Schasinglulu pnc_context_t *pnc_ctx); 77*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 78*91f16700Schasinglulu 79*91f16700Schasinglulu #endif /* __PNCD_PRIVATE_H__ */ 80