xref: /arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
4*91f16700Schasinglulu  *
5*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
6*91f16700Schasinglulu  */
7*91f16700Schasinglulu 
8*91f16700Schasinglulu #ifndef ZYNQMP_PM_API_SYS_H
9*91f16700Schasinglulu #define ZYNQMP_PM_API_SYS_H
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #include <stdint.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu #include "pm_defs.h"
14*91f16700Schasinglulu #include "zynqmp_pm_defs.h"
15*91f16700Schasinglulu 
16*91f16700Schasinglulu enum pm_query_ids {
17*91f16700Schasinglulu 	PM_QID_INVALID,
18*91f16700Schasinglulu 	PM_QID_CLOCK_GET_NAME,
19*91f16700Schasinglulu 	PM_QID_CLOCK_GET_TOPOLOGY,
20*91f16700Schasinglulu 	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
21*91f16700Schasinglulu 	PM_QID_CLOCK_GET_PARENTS,
22*91f16700Schasinglulu 	PM_QID_CLOCK_GET_ATTRIBUTES,
23*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_NUM_PINS,
24*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
25*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
26*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_FUNCTION_NAME,
27*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
28*91f16700Schasinglulu 	PM_QID_PINCTRL_GET_PIN_GROUPS,
29*91f16700Schasinglulu 	PM_QID_CLOCK_GET_NUM_CLOCKS,
30*91f16700Schasinglulu 	PM_QID_CLOCK_GET_MAX_DIVISOR,
31*91f16700Schasinglulu };
32*91f16700Schasinglulu 
33*91f16700Schasinglulu enum pm_register_access_id {
34*91f16700Schasinglulu 	CONFIG_REG_WRITE,
35*91f16700Schasinglulu 	CONFIG_REG_READ,
36*91f16700Schasinglulu };
37*91f16700Schasinglulu 
38*91f16700Schasinglulu /*
39*91f16700Schasinglulu  * Assigning of argument values into array elements.
40*91f16700Schasinglulu  */
41*91f16700Schasinglulu #define PM_PACK_PAYLOAD1(pl, arg0) {	\
42*91f16700Schasinglulu 	pl[0] = (uint32_t)(arg0);	\
43*91f16700Schasinglulu }
44*91f16700Schasinglulu 
45*91f16700Schasinglulu #define PM_PACK_PAYLOAD2(pl, arg0, arg1) {	\
46*91f16700Schasinglulu 	pl[1] = (uint32_t)(arg1);		\
47*91f16700Schasinglulu 	PM_PACK_PAYLOAD1(pl, arg0);		\
48*91f16700Schasinglulu }
49*91f16700Schasinglulu 
50*91f16700Schasinglulu #define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) {	\
51*91f16700Schasinglulu 	pl[2] = (uint32_t)(arg2);			\
52*91f16700Schasinglulu 	PM_PACK_PAYLOAD2(pl, arg0, arg1);		\
53*91f16700Schasinglulu }
54*91f16700Schasinglulu 
55*91f16700Schasinglulu #define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) {	\
56*91f16700Schasinglulu 	pl[3] = (uint32_t)(arg3);			\
57*91f16700Schasinglulu 	PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2);		\
58*91f16700Schasinglulu }
59*91f16700Schasinglulu 
60*91f16700Schasinglulu #define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) {	\
61*91f16700Schasinglulu 	pl[4] = (uint32_t)(arg4);				\
62*91f16700Schasinglulu 	PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3);		\
63*91f16700Schasinglulu }
64*91f16700Schasinglulu 
65*91f16700Schasinglulu #define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) {	\
66*91f16700Schasinglulu 	pl[5] = (uint32_t)(arg5);					\
67*91f16700Schasinglulu 	PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4);		\
68*91f16700Schasinglulu }
69*91f16700Schasinglulu 
70*91f16700Schasinglulu /**********************************************************
71*91f16700Schasinglulu  * System-level API function declarations
72*91f16700Schasinglulu  **********************************************************/
73*91f16700Schasinglulu enum pm_ret_status pm_req_suspend(enum pm_node_id target,
74*91f16700Schasinglulu 				  enum pm_request_ack ack,
75*91f16700Schasinglulu 				  uint32_t latency,
76*91f16700Schasinglulu 				  uint32_t state);
77*91f16700Schasinglulu 
78*91f16700Schasinglulu enum pm_ret_status pm_self_suspend(enum pm_node_id nid,
79*91f16700Schasinglulu 				   uint32_t latency,
80*91f16700Schasinglulu 				   uint32_t state,
81*91f16700Schasinglulu 				   uintptr_t address);
82*91f16700Schasinglulu 
83*91f16700Schasinglulu enum pm_ret_status pm_force_powerdown(enum pm_node_id target,
84*91f16700Schasinglulu 				      enum pm_request_ack ack);
85*91f16700Schasinglulu 
86*91f16700Schasinglulu enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason);
87*91f16700Schasinglulu 
88*91f16700Schasinglulu enum pm_ret_status pm_req_wakeup(enum pm_node_id target,
89*91f16700Schasinglulu 				 uint32_t set_address,
90*91f16700Schasinglulu 				 uintptr_t address,
91*91f16700Schasinglulu 				 enum pm_request_ack ack);
92*91f16700Schasinglulu 
93*91f16700Schasinglulu enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target,
94*91f16700Schasinglulu 					enum pm_node_id wkup_node,
95*91f16700Schasinglulu 					uint32_t enable);
96*91f16700Schasinglulu 
97*91f16700Schasinglulu enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype);
98*91f16700Schasinglulu 
99*91f16700Schasinglulu /* API functions for managing PM Slaves */
100*91f16700Schasinglulu enum pm_ret_status pm_req_node(enum pm_node_id nid,
101*91f16700Schasinglulu 			       uint32_t capabilities,
102*91f16700Schasinglulu 			       uint32_t qos,
103*91f16700Schasinglulu 			       enum pm_request_ack ack);
104*91f16700Schasinglulu 
105*91f16700Schasinglulu enum pm_ret_status pm_set_requirement(enum pm_node_id nid,
106*91f16700Schasinglulu 				      uint32_t capabilities,
107*91f16700Schasinglulu 				      uint32_t qos,
108*91f16700Schasinglulu 				      enum pm_request_ack ack);
109*91f16700Schasinglulu 
110*91f16700Schasinglulu /* Miscellaneous API functions */
111*91f16700Schasinglulu enum pm_ret_status pm_get_api_version(uint32_t *version);
112*91f16700Schasinglulu enum pm_ret_status pm_get_node_status(enum pm_node_id nid,
113*91f16700Schasinglulu 				      uint32_t *ret_buff);
114*91f16700Schasinglulu 
115*91f16700Schasinglulu /* Direct-Control API functions */
116*91f16700Schasinglulu enum pm_ret_status pm_mmio_write(uintptr_t address,
117*91f16700Schasinglulu 				 uint32_t mask,
118*91f16700Schasinglulu 				 uint32_t value);
119*91f16700Schasinglulu enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value);
120*91f16700Schasinglulu enum pm_ret_status pm_fpga_load(uint32_t address_low,
121*91f16700Schasinglulu 				uint32_t address_high,
122*91f16700Schasinglulu 				uint32_t size,
123*91f16700Schasinglulu 				uint32_t flags);
124*91f16700Schasinglulu enum pm_ret_status pm_fpga_get_status(uint32_t *value);
125*91f16700Schasinglulu 
126*91f16700Schasinglulu enum pm_ret_status pm_get_chipid(uint32_t *value);
127*91f16700Schasinglulu enum pm_ret_status pm_secure_rsaaes(uint32_t address_low,
128*91f16700Schasinglulu 				    uint32_t address_high,
129*91f16700Schasinglulu 				    uint32_t size,
130*91f16700Schasinglulu 				    uint32_t flags);
131*91f16700Schasinglulu uint32_t pm_get_shutdown_scope(void);
132*91f16700Schasinglulu enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count);
133*91f16700Schasinglulu enum pm_ret_status pm_ioctl(enum pm_node_id nid,
134*91f16700Schasinglulu 			    uint32_t ioctl_id,
135*91f16700Schasinglulu 			    uint32_t arg1,
136*91f16700Schasinglulu 			    uint32_t arg2,
137*91f16700Schasinglulu 			    uint32_t *value);
138*91f16700Schasinglulu enum pm_ret_status pm_clock_enable(uint32_t clock_id);
139*91f16700Schasinglulu enum pm_ret_status pm_clock_disable(uint32_t clock_id);
140*91f16700Schasinglulu enum pm_ret_status pm_clock_getstate(uint32_t clock_id,
141*91f16700Schasinglulu 				     uint32_t *state);
142*91f16700Schasinglulu enum pm_ret_status pm_clock_setdivider(uint32_t clock_id,
143*91f16700Schasinglulu 				       uint32_t divider);
144*91f16700Schasinglulu enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
145*91f16700Schasinglulu 				       uint32_t *divider);
146*91f16700Schasinglulu enum pm_ret_status pm_clock_setparent(uint32_t clock_id,
147*91f16700Schasinglulu 				      uint32_t parent_index);
148*91f16700Schasinglulu enum pm_ret_status pm_clock_getparent(uint32_t clock_id,
149*91f16700Schasinglulu 				      uint32_t *parent_index);
150*91f16700Schasinglulu void pm_query_data(enum pm_query_ids qid, uint32_t arg1, uint32_t arg2,
151*91f16700Schasinglulu 		   uint32_t arg3, uint32_t *data);
152*91f16700Schasinglulu enum pm_ret_status pm_sha_hash(uint32_t address_high,
153*91f16700Schasinglulu 				    uint32_t address_low,
154*91f16700Schasinglulu 				    uint32_t size,
155*91f16700Schasinglulu 				    uint32_t flags);
156*91f16700Schasinglulu enum pm_ret_status pm_rsa_core(uint32_t address_high,
157*91f16700Schasinglulu 				    uint32_t address_low,
158*91f16700Schasinglulu 				    uint32_t size,
159*91f16700Schasinglulu 				    uint32_t flags);
160*91f16700Schasinglulu enum pm_ret_status pm_secure_image(uint32_t address_low,
161*91f16700Schasinglulu 				   uint32_t address_high,
162*91f16700Schasinglulu 				   uint32_t key_lo,
163*91f16700Schasinglulu 				   uint32_t key_hi,
164*91f16700Schasinglulu 				   uint32_t *value);
165*91f16700Schasinglulu enum pm_ret_status pm_fpga_read(uint32_t reg_numframes,
166*91f16700Schasinglulu 				uint32_t address_low,
167*91f16700Schasinglulu 				uint32_t address_high,
168*91f16700Schasinglulu 				uint32_t readback_type,
169*91f16700Schasinglulu 				uint32_t *value);
170*91f16700Schasinglulu enum pm_ret_status pm_aes_engine(uint32_t address_high,
171*91f16700Schasinglulu 				 uint32_t address_low,
172*91f16700Schasinglulu 				 uint32_t  *value);
173*91f16700Schasinglulu enum pm_ret_status pm_register_access(uint32_t register_access_id,
174*91f16700Schasinglulu 				      uint32_t address,
175*91f16700Schasinglulu 				      uint32_t mask,
176*91f16700Schasinglulu 				      uint32_t value,
177*91f16700Schasinglulu 				      uint32_t *out);
178*91f16700Schasinglulu enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
179*91f16700Schasinglulu 					enum pm_pll_param param_id,
180*91f16700Schasinglulu 					uint32_t value);
181*91f16700Schasinglulu enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
182*91f16700Schasinglulu 					enum pm_pll_param param_id,
183*91f16700Schasinglulu 					uint32_t *value);
184*91f16700Schasinglulu enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode);
185*91f16700Schasinglulu enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode);
186*91f16700Schasinglulu enum pm_ret_status pm_efuse_access(uint32_t address_high,
187*91f16700Schasinglulu 				   uint32_t address_low, uint32_t *value);
188*91f16700Schasinglulu enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
189*91f16700Schasinglulu 				    uint32_t *bit_mask, uint8_t len);
190*91f16700Schasinglulu enum pm_ret_status check_api_dependency(uint8_t id);
191*91f16700Schasinglulu 
192*91f16700Schasinglulu #endif /* ZYNQMP_PM_API_SYS_H */
193