1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* 9*91f16700Schasinglulu * ZynqMP system level PM-API functions for pin control. 10*91f16700Schasinglulu */ 11*91f16700Schasinglulu 12*91f16700Schasinglulu #ifndef PM_API_IOCTL_H 13*91f16700Schasinglulu #define PM_API_IOCTL_H 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include "pm_common.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu //RPU operation mode 18*91f16700Schasinglulu #define PM_RPU_MODE_LOCKSTEP 0U 19*91f16700Schasinglulu #define PM_RPU_MODE_SPLIT 1U 20*91f16700Schasinglulu 21*91f16700Schasinglulu //RPU boot mem 22*91f16700Schasinglulu #define PM_RPU_BOOTMEM_LOVEC 0U 23*91f16700Schasinglulu #define PM_RPU_BOOTMEM_HIVEC 1U 24*91f16700Schasinglulu 25*91f16700Schasinglulu //RPU tcm mpde 26*91f16700Schasinglulu #define PM_RPU_TCM_SPLIT 0U 27*91f16700Schasinglulu #define PM_RPU_TCM_COMB 1U 28*91f16700Schasinglulu 29*91f16700Schasinglulu //tap delay signal type 30*91f16700Schasinglulu #define PM_TAPDELAY_NAND_DQS_IN 0U 31*91f16700Schasinglulu #define PM_TAPDELAY_NAND_DQS_OUT 1U 32*91f16700Schasinglulu #define PM_TAPDELAY_QSPI 2U 33*91f16700Schasinglulu #define PM_TAPDELAY_MAX 3U 34*91f16700Schasinglulu 35*91f16700Schasinglulu //tap delay bypass 36*91f16700Schasinglulu #define PM_TAPDELAY_BYPASS_DISABLE 0U 37*91f16700Schasinglulu #define PM_TAPDELAY_BYPASS_ENABLE 1U 38*91f16700Schasinglulu 39*91f16700Schasinglulu enum tap_delay_type { 40*91f16700Schasinglulu PM_TAPDELAY_INPUT, 41*91f16700Schasinglulu PM_TAPDELAY_OUTPUT, 42*91f16700Schasinglulu }; 43*91f16700Schasinglulu 44*91f16700Schasinglulu //dll reset type 45*91f16700Schasinglulu #define PM_DLL_RESET_ASSERT 0U 46*91f16700Schasinglulu #define PM_DLL_RESET_RELEASE 1U 47*91f16700Schasinglulu #define PM_DLL_RESET_PULSE 2U 48*91f16700Schasinglulu 49*91f16700Schasinglulu enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 50*91f16700Schasinglulu uint32_t ioctl_id, 51*91f16700Schasinglulu uint32_t arg1, 52*91f16700Schasinglulu uint32_t arg2, 53*91f16700Schasinglulu uint32_t *value); 54*91f16700Schasinglulu enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask); 55*91f16700Schasinglulu #endif /* PM_API_IOCTL_H */ 56