1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PLAT_PRIVATE_H 9*91f16700Schasinglulu #define PLAT_PRIVATE_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <bl31/interrupt_mgmt.h> 14*91f16700Schasinglulu #include <common/bl_common.h> 15*91f16700Schasinglulu #include <drivers/cadence/cdns_uart.h> 16*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu void zynqmp_config_setup(void); 19*91f16700Schasinglulu 20*91f16700Schasinglulu const mmap_region_t *plat_get_mmap(void); 21*91f16700Schasinglulu 22*91f16700Schasinglulu uint32_t zynqmp_calc_core_pos(u_register_t mpidr); 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* ZynqMP specific functions */ 25*91f16700Schasinglulu uint32_t get_uart_clk(void); 26*91f16700Schasinglulu uint32_t zynqmp_get_bootmode(void); 27*91f16700Schasinglulu 28*91f16700Schasinglulu #if ZYNQMP_WDT_RESTART 29*91f16700Schasinglulu typedef struct zynqmp_intr_info_type_el3 { 30*91f16700Schasinglulu uint32_t id; 31*91f16700Schasinglulu interrupt_type_handler_t handler; 32*91f16700Schasinglulu } zynmp_intr_info_type_el3_t; 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* 35*91f16700Schasinglulu * Register handler to specific GIC entrance 36*91f16700Schasinglulu * for INTR_TYPE_EL3 type of interrupt 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu int request_intr_type_el3(uint32_t, interrupt_type_handler_t); 39*91f16700Schasinglulu #endif 40*91f16700Schasinglulu 41*91f16700Schasinglulu #endif /* PLAT_PRIVATE_H */ 42