1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu /* ZynqMP IPI management enums and defines */ 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifndef PLAT_IPI_H 12*91f16700Schasinglulu #define PLAT_IPI_H 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <stdint.h> 15*91f16700Schasinglulu #include <ipi.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /********************************************************************* 18*91f16700Schasinglulu * IPI agent IDs macros 19*91f16700Schasinglulu ********************************************************************/ 20*91f16700Schasinglulu #define IPI_ID_APU 0U 21*91f16700Schasinglulu #define IPI_ID_RPU0 1U 22*91f16700Schasinglulu #define IPI_ID_RPU1 2U 23*91f16700Schasinglulu #define IPI_ID_PMU0 3U 24*91f16700Schasinglulu #define IPI_ID_PMU1 4U 25*91f16700Schasinglulu #define IPI_ID_PMU2 5U 26*91f16700Schasinglulu #define IPI_ID_PMU3 6U 27*91f16700Schasinglulu #define IPI_ID_PL0 7U 28*91f16700Schasinglulu #define IPI_ID_PL1 8U 29*91f16700Schasinglulu #define IPI_ID_PL2 9U 30*91f16700Schasinglulu #define IPI_ID_PL3 10U 31*91f16700Schasinglulu 32*91f16700Schasinglulu /********************************************************************* 33*91f16700Schasinglulu * IPI message buffers 34*91f16700Schasinglulu ********************************************************************/ 35*91f16700Schasinglulu #define IPI_BUFFER_BASEADDR 0xFF990000U 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define IPI_LOCAL_ID IPI_ID_APU 38*91f16700Schasinglulu #define IPI_REMOTE_ID IPI_ID_PMU0 39*91f16700Schasinglulu 40*91f16700Schasinglulu #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U) 41*91f16700Schasinglulu #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0xE00U) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U 44*91f16700Schasinglulu #define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U 45*91f16700Schasinglulu 46*91f16700Schasinglulu #define IPI_BUFFER_MAX_WORDS 8U 47*91f16700Schasinglulu 48*91f16700Schasinglulu #define IPI_BUFFER_REQ_OFFSET 0x0U 49*91f16700Schasinglulu #define IPI_BUFFER_RESP_OFFSET 0x20U 50*91f16700Schasinglulu 51*91f16700Schasinglulu /********************************************************************* 52*91f16700Schasinglulu * Platform specific IPI API declarations 53*91f16700Schasinglulu ********************************************************************/ 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* Configure IPI table for zynqmp */ 56*91f16700Schasinglulu void zynqmp_ipi_config_table_init(void); 57*91f16700Schasinglulu 58*91f16700Schasinglulu #endif /* PLAT_IPI_H */ 59