1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 12*91f16700Schasinglulu .globl plat_is_my_cpu_primary 13*91f16700Schasinglulu .globl zynqmp_calc_core_pos 14*91f16700Schasinglulu .globl plat_my_core_pos 15*91f16700Schasinglulu .globl platform_mem_init 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ----------------------------------------------------- 18*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 19*91f16700Schasinglulu * 20*91f16700Schasinglulu * This function performs any platform specific actions 21*91f16700Schasinglulu * needed for a secondary cpu after a cold reset e.g 22*91f16700Schasinglulu * mark the cpu's presence, mechanism to place it in a 23*91f16700Schasinglulu * holding pen etc. 24*91f16700Schasinglulu * TODO: Should we read the PSYS register to make sure 25*91f16700Schasinglulu * that the request has gone through. 26*91f16700Schasinglulu * ----------------------------------------------------- 27*91f16700Schasinglulu */ 28*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 29*91f16700Schasinglulu mrs x0, mpidr_el1 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* Deactivate the gic cpu interface */ 32*91f16700Schasinglulu ldr x1, =BASE_GICC_BASE 33*91f16700Schasinglulu mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) 34*91f16700Schasinglulu orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) 35*91f16700Schasinglulu str w0, [x1, #GICC_CTLR] 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* 38*91f16700Schasinglulu * There is no sane reason to come out of this wfi. This 39*91f16700Schasinglulu * cpu will be powered on and reset by the cpu_on pm api 40*91f16700Schasinglulu */ 41*91f16700Schasinglulu dsb sy 42*91f16700Schasinglulu1: 43*91f16700Schasinglulu no_ret plat_panic_handler 44*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 45*91f16700Schasinglulu 46*91f16700Schasinglulufunc plat_is_my_cpu_primary 47*91f16700Schasinglulu mov x9, x30 48*91f16700Schasinglulu bl plat_my_core_pos 49*91f16700Schasinglulu cmp x0, #ZYNQMP_PRIMARY_CPU 50*91f16700Schasinglulu cset x0, eq 51*91f16700Schasinglulu ret x9 52*91f16700Schasingluluendfunc plat_is_my_cpu_primary 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* ----------------------------------------------------- 55*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 56*91f16700Schasinglulu * This function uses the zynqmp_calc_core_pos() 57*91f16700Schasinglulu * definition to get the index of the calling CPU. 58*91f16700Schasinglulu * ----------------------------------------------------- 59*91f16700Schasinglulu */ 60*91f16700Schasinglulufunc plat_my_core_pos 61*91f16700Schasinglulu mrs x0, mpidr_el1 62*91f16700Schasinglulu b zynqmp_calc_core_pos 63*91f16700Schasingluluendfunc plat_my_core_pos 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* ----------------------------------------------------- 66*91f16700Schasinglulu * unsigned int zynqmp_calc_core_pos(u_register_t mpidr) 67*91f16700Schasinglulu * Helper function to calculate the core position. 68*91f16700Schasinglulu * With this function: CorePos = (ClusterId * 4) + 69*91f16700Schasinglulu * CoreId 70*91f16700Schasinglulu * ----------------------------------------------------- 71*91f16700Schasinglulu */ 72*91f16700Schasinglulufunc zynqmp_calc_core_pos 73*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 74*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 75*91f16700Schasinglulu add x0, x1, x0, LSR #6 76*91f16700Schasinglulu ret 77*91f16700Schasingluluendfunc zynqmp_calc_core_pos 78*91f16700Schasinglulu 79*91f16700Schasinglulu /* --------------------------------------------------------------------- 80*91f16700Schasinglulu * We don't need to carry out any memory initialization on ARM 81*91f16700Schasinglulu * platforms. The Secure RAM is accessible straight away. 82*91f16700Schasinglulu * --------------------------------------------------------------------- 83*91f16700Schasinglulu */ 84*91f16700Schasinglulufunc platform_mem_init 85*91f16700Schasinglulu ret 86*91f16700Schasingluluendfunc platform_mem_init 87