1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*91f16700Schasinglulu * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <plat/common/platform.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <plat_private.h> 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu static const uint8_t plat_power_domain_tree_desc[] = { 16*91f16700Schasinglulu /* Number of root nodes */ 17*91f16700Schasinglulu 1, 18*91f16700Schasinglulu /* Number of clusters */ 19*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT, 20*91f16700Schasinglulu /* Number of children for the first cluster node */ 21*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER, 22*91f16700Schasinglulu /* Number of children for the second cluster node */ 23*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER, 24*91f16700Schasinglulu /* Number of children for the third cluster node */ 25*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER, 26*91f16700Schasinglulu /* Number of children for the fourth cluster node */ 27*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER, 28*91f16700Schasinglulu }; 29*91f16700Schasinglulu 30*91f16700Schasinglulu const uint8_t *plat_get_power_domain_tree_desc(void) 31*91f16700Schasinglulu { 32*91f16700Schasinglulu return plat_power_domain_tree_desc; 33*91f16700Schasinglulu } 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * This function implements a part of the critical interface between the psci 37*91f16700Schasinglulu * generic layer and the platform that allows the former to query the platform 38*91f16700Schasinglulu * to convert an MPIDR to a unique linear index. An error code (-1) is returned 39*91f16700Schasinglulu * in case the MPIDR is invalid. 40*91f16700Schasinglulu ******************************************************************************/ 41*91f16700Schasinglulu int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu uint32_t cluster_id, cpu_id; 44*91f16700Schasinglulu 45*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 46*91f16700Schasinglulu 47*91f16700Schasinglulu cluster_id = MPIDR_AFFLVL2_VAL(mpidr); 48*91f16700Schasinglulu cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 49*91f16700Schasinglulu 50*91f16700Schasinglulu if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 51*91f16700Schasinglulu return -3; 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* 55*91f16700Schasinglulu * Validate cpu_id by checking whether it represents a CPU in 56*91f16700Schasinglulu * one of the two clusters present on the platform. 57*91f16700Schasinglulu */ 58*91f16700Schasinglulu if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { 59*91f16700Schasinglulu return -1; 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); 63*91f16700Schasinglulu } 64