1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu#ifndef PLAT_MACROS_S 10*91f16700Schasinglulu#define PLAT_MACROS_S 11*91f16700Schasinglulu 12*91f16700Schasinglulu#include <drivers/arm/gic_common.h> 13*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 14*91f16700Schasinglulu#include <drivers/arm/gicv3.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu#include "../include/platform_def.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu.section .rodata.gic_reg_name, "aS" 19*91f16700Schasinglulu/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 20*91f16700Schasinglulugicc_regs: 21*91f16700Schasinglulu .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 22*91f16700Schasinglulu 23*91f16700Schasinglulu/* Applicable only to GICv3 with SRE enabled */ 24*91f16700Schasingluluicc_regs: 25*91f16700Schasinglulu .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 26*91f16700Schasinglulu 27*91f16700Schasinglulu/* Registers common to both GICv2 and GICv3 */ 28*91f16700Schasinglulugicd_pend_reg: 29*91f16700Schasinglulu .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 30*91f16700Schasinglulunewline: 31*91f16700Schasinglulu .asciz "\n" 32*91f16700Schasingluluspacer: 33*91f16700Schasinglulu .asciz ":\t\t0x" 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* --------------------------------------------- 36*91f16700Schasinglulu * The below utility macro prints out relevant GIC 37*91f16700Schasinglulu * registers whenever an unhandled exception is 38*91f16700Schasinglulu * taken in BL31 on Versal NET platform. 39*91f16700Schasinglulu * Expects: GICD base in x16, GICC base in x17 40*91f16700Schasinglulu * Clobbers: x0 - x10, sp 41*91f16700Schasinglulu * --------------------------------------------- 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu .macro versal_net_print_gic_regs 44*91f16700Schasinglulu /* Check for GICv3 system register access */ 45*91f16700Schasinglulu mrs x7, id_aa64pfr0_el1 46*91f16700Schasinglulu ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 47*91f16700Schasinglulu cmp x7, #1 48*91f16700Schasinglulu b.ne print_gicv2 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* Check for SRE enable */ 51*91f16700Schasinglulu mrs x8, ICC_SRE_EL3 52*91f16700Schasinglulu tst x8, #ICC_SRE_SRE_BIT 53*91f16700Schasinglulu b.eq print_gicv2 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* Load the icc reg list to x6 */ 56*91f16700Schasinglulu adr x6, icc_regs 57*91f16700Schasinglulu /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 58*91f16700Schasinglulu mrs x8, ICC_HPPIR0_EL1 59*91f16700Schasinglulu mrs x9, ICC_HPPIR1_EL1 60*91f16700Schasinglulu mrs x10, ICC_CTLR_EL3 61*91f16700Schasinglulu /* Store to the crash buf and print to console */ 62*91f16700Schasinglulu bl str_in_crash_buf_print 63*91f16700Schasinglulu b print_gic_common 64*91f16700Schasinglulu 65*91f16700Schasingluluprint_gicv2: 66*91f16700Schasinglulu /* Load the gicc reg list to x6 */ 67*91f16700Schasinglulu adr x6, gicc_regs 68*91f16700Schasinglulu /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 69*91f16700Schasinglulu ldr w8, [x17, #GICC_HPPIR] 70*91f16700Schasinglulu ldr w9, [x17, #GICC_AHPPIR] 71*91f16700Schasinglulu ldr w10, [x17, #GICC_CTLR] 72*91f16700Schasinglulu /* Store to the crash buf and print to console */ 73*91f16700Schasinglulu bl str_in_crash_buf_print 74*91f16700Schasinglulu 75*91f16700Schasingluluprint_gic_common: 76*91f16700Schasinglulu /* Print the GICD_ISPENDR regs */ 77*91f16700Schasinglulu add x7, x16, #GICD_ISPENDR 78*91f16700Schasinglulu adr x4, gicd_pend_reg 79*91f16700Schasinglulu bl asm_print_str 80*91f16700Schasinglulugicd_ispendr_loop: 81*91f16700Schasinglulu sub x4, x7, x16 82*91f16700Schasinglulu cmp x4, #0x280 83*91f16700Schasinglulu b.eq exit_print_gic_regs 84*91f16700Schasinglulu bl asm_print_hex 85*91f16700Schasinglulu 86*91f16700Schasinglulu adr x4, spacer 87*91f16700Schasinglulu bl asm_print_str 88*91f16700Schasinglulu 89*91f16700Schasinglulu ldr x4, [x7], #8 90*91f16700Schasinglulu bl asm_print_hex 91*91f16700Schasinglulu 92*91f16700Schasinglulu adr x4, newline 93*91f16700Schasinglulu bl asm_print_str 94*91f16700Schasinglulu b gicd_ispendr_loop 95*91f16700Schasingluluexit_print_gic_regs: 96*91f16700Schasinglulu .endm 97*91f16700Schasinglulu 98*91f16700Schasinglulu /* --------------------------------------------- 99*91f16700Schasinglulu * The below required platform porting macro 100*91f16700Schasinglulu * prints out relevant GIC and CCI registers 101*91f16700Schasinglulu * whenever an unhandled exception is taken in 102*91f16700Schasinglulu * BL31. 103*91f16700Schasinglulu * Clobbers: x0 - x10, x16, x17, sp 104*91f16700Schasinglulu * --------------------------------------------- 105*91f16700Schasinglulu */ 106*91f16700Schasinglulu .macro plat_crash_print_regs 107*91f16700Schasinglulu /* 108*91f16700Schasinglulu * Empty for now to handle more platforms variant. 109*91f16700Schasinglulu * Uncomment it when versions are stable 110*91f16700Schasinglulu */ 111*91f16700Schasinglulu /* 112*91f16700Schasinglulu mov_imm x17, PLAT_GICD_BASE_VALUE 113*91f16700Schasinglulu mov_imm x16, PLAT_GICR_BASE_VALUE 114*91f16700Schasinglulu versal_net_print_gic_regs 115*91f16700Schasinglulu */ 116*91f16700Schasinglulu .endm 117*91f16700Schasinglulu 118*91f16700Schasinglulu#endif /* PLAT_MACROS_S */ 119