1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <arch.h> 10*91f16700Schasinglulu#include <asm_macros.S> 11*91f16700Schasinglulu#include <drivers/arm/gicv3.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu#include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 16*91f16700Schasinglulu .globl plat_is_my_cpu_primary 17*91f16700Schasinglulu .globl platform_mem_init 18*91f16700Schasinglulu .globl plat_my_core_pos 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* ----------------------------------------------------- 21*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 22*91f16700Schasinglulu * 23*91f16700Schasinglulu * This function performs any platform specific actions 24*91f16700Schasinglulu * needed for a secondary cpu after a cold reset e.g 25*91f16700Schasinglulu * mark the cpu's presence, mechanism to place it in a 26*91f16700Schasinglulu * holding pen etc. 27*91f16700Schasinglulu * TODO: Should we read the PSYS register to make sure 28*91f16700Schasinglulu * that the request has gone through. 29*91f16700Schasinglulu * ----------------------------------------------------- 30*91f16700Schasinglulu */ 31*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 32*91f16700Schasinglulu mrs x0, mpidr_el1 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* 35*91f16700Schasinglulu * There is no sane reason to come out of this wfi. This 36*91f16700Schasinglulu * cpu will be powered on and reset by the cpu_on pm api 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu dsb sy 39*91f16700Schasinglulu bl plat_panic_handler 40*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 41*91f16700Schasinglulu 42*91f16700Schasinglulufunc plat_is_my_cpu_primary 43*91f16700Schasinglulu mov x9, x30 44*91f16700Schasinglulu bl plat_my_core_pos 45*91f16700Schasinglulu cmp x0, #VERSAL_NET_PRIMARY_CPU 46*91f16700Schasinglulu cset x0, eq 47*91f16700Schasinglulu ret x9 48*91f16700Schasingluluendfunc plat_is_my_cpu_primary 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* ----------------------------------------------------- 51*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 52*91f16700Schasinglulu * This function uses the plat_core_pos_by_mpidr() 53*91f16700Schasinglulu * definition to get the index of the calling CPU. 54*91f16700Schasinglulu * ----------------------------------------------------- 55*91f16700Schasinglulu */ 56*91f16700Schasinglulufunc plat_my_core_pos 57*91f16700Schasinglulu mrs x0, mpidr_el1 58*91f16700Schasinglulu b plat_core_pos_by_mpidr 59*91f16700Schasingluluendfunc plat_my_core_pos 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* --------------------------------------------------------------------- 62*91f16700Schasinglulu * We don't need to carry out any memory initialization on Versal NET 63*91f16700Schasinglulu * platform. The Secure RAM is accessible straight away. 64*91f16700Schasinglulu * --------------------------------------------------------------------- 65*91f16700Schasinglulu */ 66*91f16700Schasinglulufunc platform_mem_init 67*91f16700Schasinglulu ret 68*91f16700Schasingluluendfunc platform_mem_init 69