1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* 9*91f16700Schasinglulu * Versal IPI agent registers access management 10*91f16700Schasinglulu */ 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <lib/utils_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <ipi.h> 15*91f16700Schasinglulu #include <plat_ipi.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* versal ipi configuration table */ 18*91f16700Schasinglulu static const struct ipi_config versal_ipi_table[] = { 19*91f16700Schasinglulu /* PMC IPI */ 20*91f16700Schasinglulu [IPI_ID_PMC] = { 21*91f16700Schasinglulu .ipi_bit_mask = PMC_IPI_TRIG_BIT, 22*91f16700Schasinglulu .ipi_reg_base = PMC_REG_BASE, 23*91f16700Schasinglulu .secure_only = IPI_SECURE_MASK, 24*91f16700Schasinglulu }, 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* A72 IPI */ 27*91f16700Schasinglulu [IPI_ID_APU] = { 28*91f16700Schasinglulu .ipi_bit_mask = IPI0_TRIG_BIT, 29*91f16700Schasinglulu .ipi_reg_base = IPI0_REG_BASE, 30*91f16700Schasinglulu .secure_only = 0U, 31*91f16700Schasinglulu }, 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* RPU0 IPI */ 34*91f16700Schasinglulu [IPI_ID_RPU0] = { 35*91f16700Schasinglulu .ipi_bit_mask = IPI1_TRIG_BIT, 36*91f16700Schasinglulu .ipi_reg_base = IPI1_REG_BASE, 37*91f16700Schasinglulu .secure_only = 0U, 38*91f16700Schasinglulu }, 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* RPU1 IPI */ 41*91f16700Schasinglulu [IPI_ID_RPU1] = { 42*91f16700Schasinglulu .ipi_bit_mask = IPI2_TRIG_BIT, 43*91f16700Schasinglulu .ipi_reg_base = IPI2_REG_BASE, 44*91f16700Schasinglulu .secure_only = 0U, 45*91f16700Schasinglulu }, 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* IPI3 IPI */ 48*91f16700Schasinglulu [IPI_ID_3] = { 49*91f16700Schasinglulu .ipi_bit_mask = IPI3_TRIG_BIT, 50*91f16700Schasinglulu .ipi_reg_base = IPI3_REG_BASE, 51*91f16700Schasinglulu .secure_only = 0U, 52*91f16700Schasinglulu }, 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* IPI4 IPI */ 55*91f16700Schasinglulu [IPI_ID_4] = { 56*91f16700Schasinglulu .ipi_bit_mask = IPI4_TRIG_BIT, 57*91f16700Schasinglulu .ipi_reg_base = IPI4_REG_BASE, 58*91f16700Schasinglulu .secure_only = 0U, 59*91f16700Schasinglulu }, 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* IPI5 IPI */ 62*91f16700Schasinglulu [IPI_ID_5] = { 63*91f16700Schasinglulu .ipi_bit_mask = IPI5_TRIG_BIT, 64*91f16700Schasinglulu .ipi_reg_base = IPI5_REG_BASE, 65*91f16700Schasinglulu .secure_only = 0U, 66*91f16700Schasinglulu }, 67*91f16700Schasinglulu }; 68*91f16700Schasinglulu 69*91f16700Schasinglulu /* versal_ipi_config_table_init() - Initialize versal IPI configuration data. 70*91f16700Schasinglulu * @ipi_config_table: IPI configuration table. 71*91f16700Schasinglulu * @ipi_total: Total number of IPI available. 72*91f16700Schasinglulu * 73*91f16700Schasinglulu */ 74*91f16700Schasinglulu void versal_ipi_config_table_init(void) 75*91f16700Schasinglulu { 76*91f16700Schasinglulu ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table)); 77*91f16700Schasinglulu } 78