1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu */ 8*91f16700Schasinglulu 9*91f16700Schasinglulu #ifndef VERSAL_DEF_H 10*91f16700Schasinglulu #define VERSAL_DEF_H 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <plat/arm/common/smccc_def.h> 13*91f16700Schasinglulu #include <plat/common/common_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLATFORM_MASK GENMASK(27U, 24U) 16*91f16700Schasinglulu #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* number of interrupt handlers. increase as required */ 19*91f16700Schasinglulu #define MAX_INTR_EL3 2 20*91f16700Schasinglulu /* List all consoles */ 21*91f16700Schasinglulu #define VERSAL_CONSOLE_ID_pl011 1 22*91f16700Schasinglulu #define VERSAL_CONSOLE_ID_pl011_0 1 23*91f16700Schasinglulu #define VERSAL_CONSOLE_ID_pl011_1 2 24*91f16700Schasinglulu #define VERSAL_CONSOLE_ID_dcc 3 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* List all supported platforms */ 29*91f16700Schasinglulu #define VERSAL_PLATFORM_ID_versal_virt 1 30*91f16700Schasinglulu #define VERSAL_PLATFORM_ID_spp_itr6 2 31*91f16700Schasinglulu #define VERSAL_PLATFORM_ID_emu_itr6 3 32*91f16700Schasinglulu #define VERSAL_PLATFORM_ID_silicon 4 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* Firmware Image Package */ 37*91f16700Schasinglulu #define VERSAL_PRIMARY_CPU 0 38*91f16700Schasinglulu 39*91f16700Schasinglulu /******************************************************************************* 40*91f16700Schasinglulu * memory map related constants 41*91f16700Schasinglulu ******************************************************************************/ 42*91f16700Schasinglulu #define DEVICE0_BASE 0xFF000000 43*91f16700Schasinglulu #define DEVICE0_SIZE 0x00E00000 44*91f16700Schasinglulu #define DEVICE1_BASE 0xF9000000 45*91f16700Schasinglulu #define DEVICE1_SIZE 0x00800000 46*91f16700Schasinglulu 47*91f16700Schasinglulu /******************************************************************************* 48*91f16700Schasinglulu * IRQ constants 49*91f16700Schasinglulu ******************************************************************************/ 50*91f16700Schasinglulu #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 51*91f16700Schasinglulu #define ARM_IRQ_SEC_PHY_TIMER 29 52*91f16700Schasinglulu 53*91f16700Schasinglulu /******************************************************************************* 54*91f16700Schasinglulu * CCI-400 related constants 55*91f16700Schasinglulu ******************************************************************************/ 56*91f16700Schasinglulu #define PLAT_ARM_CCI_BASE 0xFD000000 57*91f16700Schasinglulu #define PLAT_ARM_CCI_SIZE 0x00100000 58*91f16700Schasinglulu #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 59*91f16700Schasinglulu #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 60*91f16700Schasinglulu 61*91f16700Schasinglulu /******************************************************************************* 62*91f16700Schasinglulu * UART related constants 63*91f16700Schasinglulu ******************************************************************************/ 64*91f16700Schasinglulu #define VERSAL_UART0_BASE 0xFF000000 65*91f16700Schasinglulu #define VERSAL_UART1_BASE 0xFF010000 66*91f16700Schasinglulu 67*91f16700Schasinglulu #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 68*91f16700Schasinglulu # define UART_BASE VERSAL_UART0_BASE 69*91f16700Schasinglulu #elif CONSOLE_IS(pl011_1) 70*91f16700Schasinglulu # define UART_BASE VERSAL_UART1_BASE 71*91f16700Schasinglulu #else 72*91f16700Schasinglulu # error "invalid VERSAL_CONSOLE" 73*91f16700Schasinglulu #endif 74*91f16700Schasinglulu 75*91f16700Schasinglulu /******************************************************************************* 76*91f16700Schasinglulu * Platform related constants 77*91f16700Schasinglulu ******************************************************************************/ 78*91f16700Schasinglulu #if VERSAL_PLATFORM_IS(versal_virt) 79*91f16700Schasinglulu # define PLATFORM_NAME "Versal Virt" 80*91f16700Schasinglulu # define UART_CLOCK 25000000 81*91f16700Schasinglulu # define UART_BAUDRATE 115200 82*91f16700Schasinglulu # define VERSAL_CPU_CLOCK 2720000 83*91f16700Schasinglulu #elif VERSAL_PLATFORM_IS(silicon) 84*91f16700Schasinglulu # define PLATFORM_NAME "Versal Silicon" 85*91f16700Schasinglulu # define UART_CLOCK 100000000 86*91f16700Schasinglulu # define UART_BAUDRATE 115200 87*91f16700Schasinglulu # define VERSAL_CPU_CLOCK 100000000 88*91f16700Schasinglulu #elif VERSAL_PLATFORM_IS(spp_itr6) 89*91f16700Schasinglulu # define PLATFORM_NAME "SPP ITR6" 90*91f16700Schasinglulu # define UART_CLOCK 25000000 91*91f16700Schasinglulu # define UART_BAUDRATE 115200 92*91f16700Schasinglulu # define VERSAL_CPU_CLOCK 2720000 93*91f16700Schasinglulu #elif VERSAL_PLATFORM_IS(emu_itr6) 94*91f16700Schasinglulu # define PLATFORM_NAME "EMU ITR6" 95*91f16700Schasinglulu # define UART_CLOCK 212000 96*91f16700Schasinglulu # define UART_BAUDRATE 9600 97*91f16700Schasinglulu # define VERSAL_CPU_CLOCK 212000 98*91f16700Schasinglulu #endif 99*91f16700Schasinglulu 100*91f16700Schasinglulu /* Access control register defines */ 101*91f16700Schasinglulu #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 102*91f16700Schasinglulu #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 103*91f16700Schasinglulu 104*91f16700Schasinglulu /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 105*91f16700Schasinglulu #define CRF_BASE 0xFD1A0000 106*91f16700Schasinglulu #define CRF_SIZE 0x00600000 107*91f16700Schasinglulu 108*91f16700Schasinglulu /* CRF registers and bitfields */ 109*91f16700Schasinglulu #define CRF_RST_APU (CRF_BASE + 0X00000300) 110*91f16700Schasinglulu 111*91f16700Schasinglulu #define CRF_RST_APU_ACPU_RESET (1 << 0) 112*91f16700Schasinglulu #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 113*91f16700Schasinglulu 114*91f16700Schasinglulu /* APU registers and bitfields */ 115*91f16700Schasinglulu #define FPD_APU_BASE 0xFD5C0000U 116*91f16700Schasinglulu #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 117*91f16700Schasinglulu #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 118*91f16700Schasinglulu #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 119*91f16700Schasinglulu #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 120*91f16700Schasinglulu 121*91f16700Schasinglulu #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 122*91f16700Schasinglulu #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 123*91f16700Schasinglulu #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 124*91f16700Schasinglulu 125*91f16700Schasinglulu /* PMC registers and bitfields */ 126*91f16700Schasinglulu #define PMC_GLOBAL_BASE 0xF1110000U 127*91f16700Schasinglulu #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 128*91f16700Schasinglulu 129*91f16700Schasinglulu #endif /* VERSAL_DEF_H */ 130