1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu /* Versal IPI management enums and defines */ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #ifndef PLAT_IPI_H 11*91f16700Schasinglulu #define PLAT_IPI_H 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <stdint.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <ipi.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /********************************************************************* 18*91f16700Schasinglulu * IPI agent IDs macros 19*91f16700Schasinglulu ********************************************************************/ 20*91f16700Schasinglulu #define IPI_ID_PMC 1U 21*91f16700Schasinglulu #define IPI_ID_APU 2U 22*91f16700Schasinglulu #define IPI_ID_RPU0 3U 23*91f16700Schasinglulu #define IPI_ID_RPU1 4U 24*91f16700Schasinglulu #define IPI_ID_3 5U 25*91f16700Schasinglulu #define IPI_ID_4 6U 26*91f16700Schasinglulu #define IPI_ID_5 7U 27*91f16700Schasinglulu 28*91f16700Schasinglulu /********************************************************************* 29*91f16700Schasinglulu * IPI message buffers 30*91f16700Schasinglulu ********************************************************************/ 31*91f16700Schasinglulu #define IPI_BUFFER_BASEADDR 0xFF3F0000U 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define IPI_LOCAL_ID IPI_ID_APU 34*91f16700Schasinglulu #define IPI_REMOTE_ID IPI_ID_PMC 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U)) 37*91f16700Schasinglulu #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U)) 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U) 40*91f16700Schasinglulu #define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U) 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define IPI_BUFFER_MAX_WORDS 8 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define IPI_BUFFER_REQ_OFFSET 0x0U 45*91f16700Schasinglulu #define IPI_BUFFER_RESP_OFFSET 0x20U 46*91f16700Schasinglulu 47*91f16700Schasinglulu /********************************************************************* 48*91f16700Schasinglulu * Platform specific IPI API declarations 49*91f16700Schasinglulu ********************************************************************/ 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* Configure IPI table for versal */ 52*91f16700Schasinglulu void versal_ipi_config_table_init(void); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* IPI registers and bitfields */ 55*91f16700Schasinglulu #define PMC_REG_BASE U(0xFF320000) 56*91f16700Schasinglulu #define PMC_IPI_TRIG_BIT (1U << 1U) 57*91f16700Schasinglulu #define IPI0_REG_BASE U(0xFF330000) 58*91f16700Schasinglulu #define IPI0_TRIG_BIT (1U << 2U) 59*91f16700Schasinglulu #define IPI1_REG_BASE U(0xFF340000) 60*91f16700Schasinglulu #define IPI1_TRIG_BIT (1U << 3U) 61*91f16700Schasinglulu #define IPI2_REG_BASE U(0xFF350000) 62*91f16700Schasinglulu #define IPI2_TRIG_BIT (1U << 4U) 63*91f16700Schasinglulu #define IPI3_REG_BASE U(0xFF360000) 64*91f16700Schasinglulu #define IPI3_TRIG_BIT (1U << 5U) 65*91f16700Schasinglulu #define IPI4_REG_BASE U(0xFF370000) 66*91f16700Schasinglulu #define IPI4_TRIG_BIT (1U << 5U) 67*91f16700Schasinglulu #define IPI5_REG_BASE U(0xFF380000) 68*91f16700Schasinglulu #define IPI5_TRIG_BIT (1U << 6U) 69*91f16700Schasinglulu 70*91f16700Schasinglulu #endif /* PLAT_IPI_H */ 71