1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <drivers/generic_delay_timer.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 12*91f16700Schasinglulu #include <plat/common/platform.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <plat_common.h> 15*91f16700Schasinglulu #include <plat_ipi.h> 16*91f16700Schasinglulu #include <plat_private.h> 17*91f16700Schasinglulu #include <pm_api_sys.h> 18*91f16700Schasinglulu #include <versal_def.h> 19*91f16700Schasinglulu 20*91f16700Schasinglulu uint32_t platform_id, platform_version; 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* 23*91f16700Schasinglulu * Table of regions to map using the MMU. 24*91f16700Schasinglulu * This doesn't include TZRAM as the 'mem_layout' argument passed to 25*91f16700Schasinglulu * configure_mmu_elx() will give the available subset of that, 26*91f16700Schasinglulu */ 27*91f16700Schasinglulu const mmap_region_t plat_versal_mmap[] = { 28*91f16700Schasinglulu MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 29*91f16700Schasinglulu MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 30*91f16700Schasinglulu MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 31*91f16700Schasinglulu MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW | 32*91f16700Schasinglulu MT_SECURE), 33*91f16700Schasinglulu { 0 } 34*91f16700Schasinglulu }; 35*91f16700Schasinglulu 36*91f16700Schasinglulu const mmap_region_t *plat_get_mmap(void) 37*91f16700Schasinglulu { 38*91f16700Schasinglulu return plat_versal_mmap; 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu static void versal_print_platform_name(void) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu NOTICE("TF-A running on %s\n", PLATFORM_NAME); 44*91f16700Schasinglulu } 45*91f16700Schasinglulu 46*91f16700Schasinglulu void versal_config_setup(void) 47*91f16700Schasinglulu { 48*91f16700Schasinglulu /* Configure IPI data for versal */ 49*91f16700Schasinglulu versal_ipi_config_table_init(); 50*91f16700Schasinglulu 51*91f16700Schasinglulu versal_print_platform_name(); 52*91f16700Schasinglulu 53*91f16700Schasinglulu generic_delay_timer_init(); 54*91f16700Schasinglulu } 55*91f16700Schasinglulu 56*91f16700Schasinglulu uint32_t plat_get_syscnt_freq2(void) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu return VERSAL_CPU_CLOCK; 59*91f16700Schasinglulu } 60*91f16700Schasinglulu 61*91f16700Schasinglulu void board_detection(void) 62*91f16700Schasinglulu { 63*91f16700Schasinglulu uint32_t plat_info[2]; 64*91f16700Schasinglulu 65*91f16700Schasinglulu if (pm_get_chipid(plat_info) != PM_RET_SUCCESS) { 66*91f16700Schasinglulu /* If the call is failed we cannot proceed with further 67*91f16700Schasinglulu * setup. TF-A to panic in this situation. 68*91f16700Schasinglulu */ 69*91f16700Schasinglulu NOTICE("Failed to read the chip information"); 70*91f16700Schasinglulu panic(); 71*91f16700Schasinglulu } 72*91f16700Schasinglulu 73*91f16700Schasinglulu platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]); 74*91f16700Schasinglulu platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]); 75*91f16700Schasinglulu } 76*91f16700Schasinglulu 77*91f16700Schasinglulu uint32_t get_uart_clk(void) 78*91f16700Schasinglulu { 79*91f16700Schasinglulu return UART_CLOCK; 80*91f16700Schasinglulu } 81