1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2023, Advanced Micro Devices. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <common/bl_common.h> 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <drivers/arm/pl011.h> 11*91f16700Schasinglulu #include <drivers/console.h> 12*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 13*91f16700Schasinglulu #include <platform_tsp.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <plat_private.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * Initialize the UART 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu void tsp_early_platform_setup(void) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu /* 23*91f16700Schasinglulu * Register a different console than already in use to display 24*91f16700Schasinglulu * messages from TSP 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu static console_t tsp_boot_console; 27*91f16700Schasinglulu int32_t rc; 28*91f16700Schasinglulu 29*91f16700Schasinglulu #if defined(PLAT_zynqmp) 30*91f16700Schasinglulu rc = console_cdns_register((uintptr_t)UART_BASE, 31*91f16700Schasinglulu (uint32_t)get_uart_clk(), 32*91f16700Schasinglulu (uint32_t)UART_BAUDRATE, 33*91f16700Schasinglulu &tsp_boot_console); 34*91f16700Schasinglulu #else 35*91f16700Schasinglulu rc = console_pl011_register((uintptr_t)UART_BASE, 36*91f16700Schasinglulu (uint32_t)get_uart_clk(), 37*91f16700Schasinglulu (uint32_t)UART_BAUDRATE, 38*91f16700Schasinglulu &tsp_boot_console); 39*91f16700Schasinglulu #endif 40*91f16700Schasinglulu 41*91f16700Schasinglulu if (rc == 0) { 42*91f16700Schasinglulu panic(); 43*91f16700Schasinglulu } 44*91f16700Schasinglulu 45*91f16700Schasinglulu console_set_scope(&tsp_boot_console, 46*91f16700Schasinglulu CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu /******************************************************************************* 50*91f16700Schasinglulu * Perform platform specific setup placeholder 51*91f16700Schasinglulu ******************************************************************************/ 52*91f16700Schasinglulu void tsp_platform_setup(void) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu /* 55*91f16700Schasinglulu * For ZynqMP, the GICv2 driver needs to be initialized in S-EL1, 56*91f16700Schasinglulu * and for other platforms, the GICv3 driver is initialized in EL3. 57*91f16700Schasinglulu * This is because S-EL1 can use GIC system registers to manage 58*91f16700Schasinglulu * interrupts and does not need to be initialized again in SEL1. 59*91f16700Schasinglulu */ 60*91f16700Schasinglulu #if defined(PLAT_zynqmp) 61*91f16700Schasinglulu plat_arm_gic_driver_init(); 62*91f16700Schasinglulu plat_arm_gic_init(); 63*91f16700Schasinglulu #endif 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu /******************************************************************************* 67*91f16700Schasinglulu * Perform the very early platform specific architectural setup here. At the 68*91f16700Schasinglulu * moment this is only initializes the MMU 69*91f16700Schasinglulu ******************************************************************************/ 70*91f16700Schasinglulu void tsp_plat_arch_setup(void) 71*91f16700Schasinglulu { 72*91f16700Schasinglulu const mmap_region_t bl_regions[] = { 73*91f16700Schasinglulu MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE, 74*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE), 75*91f16700Schasinglulu MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 76*91f16700Schasinglulu MT_CODE | MT_SECURE), 77*91f16700Schasinglulu MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 78*91f16700Schasinglulu MT_RO_DATA | MT_SECURE), 79*91f16700Schasinglulu #if defined(PLAT_zynqmp) || defined(PLAT_versal) 80*91f16700Schasinglulu MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 81*91f16700Schasinglulu BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 82*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 83*91f16700Schasinglulu #endif 84*91f16700Schasinglulu {0} 85*91f16700Schasinglulu }; 86*91f16700Schasinglulu 87*91f16700Schasinglulu setup_page_tables(bl_regions, plat_get_mmap()); 88*91f16700Schasinglulu enable_mmu_el1(0); 89*91f16700Schasinglulu } 90