1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef BOARD_DEF_H 8*91f16700Schasinglulu #define BOARD_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* The ports must be in order and contiguous */ 13*91f16700Schasinglulu #define K3_CLUSTER0_CORE_COUNT U(4) 14*91f16700Schasinglulu #define K3_CLUSTER1_CORE_COUNT U(4) 15*91f16700Schasinglulu #define K3_CLUSTER2_CORE_COUNT U(0) 16*91f16700Schasinglulu #define K3_CLUSTER3_CORE_COUNT U(0) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define PLAT_PROC_START_ID U(32) 19*91f16700Schasinglulu #define PLAT_PROC_DEVICE_START_ID U(202) 20*91f16700Schasinglulu #define PLAT_CLUSTER_DEVICE_START_ID U(198) 21*91f16700Schasinglulu #define PLAT_BOARD_DEVICE_ID U(157) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #endif /* BOARD_DEF_H */ 24