1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu #include <plat/common/common_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include "../stm32mp2_def.h" 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * Generic platform constants 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* Size of cacheable stacks */ 21*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0xC00 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define STM32MP_PRIMARY_CPU U(0x0) 24*91f16700Schasinglulu #define STM32MP_SECONDARY_CPU U(0x1) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define MAX_IO_DEVICES U(4) 27*91f16700Schasinglulu #define MAX_IO_HANDLES U(4) 28*91f16700Schasinglulu #define MAX_IO_BLOCK_DEVICES U(1) 29*91f16700Schasinglulu #define MAX_IO_MTD_DEVICES U(1) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(1) 32*91f16700Schasinglulu #define PLATFORM_CORE_COUNT U(2) 33*91f16700Schasinglulu #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL U(5) 36*91f16700Schasinglulu #define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5) 37*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS U(7) 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Local power state for power domains in Run state. */ 40*91f16700Schasinglulu #define STM32MP_LOCAL_STATE_RUN U(0) 41*91f16700Schasinglulu /* Local power state for retention. */ 42*91f16700Schasinglulu #define STM32MP_LOCAL_STATE_RET U(1) 43*91f16700Schasinglulu #define STM32MP_LOCAL_STATE_LP U(2) 44*91f16700Schasinglulu #define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP 45*91f16700Schasinglulu /* Local power state for OFF/power-down. */ 46*91f16700Schasinglulu #define STM32MP_LOCAL_STATE_OFF U(3) 47*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Macros to parse the state information from State-ID (recommended encoding) */ 50*91f16700Schasinglulu #define PLAT_LOCAL_PSTATE_WIDTH U(4) 51*91f16700Schasinglulu #define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) 52*91f16700Schasinglulu 53*91f16700Schasinglulu /******************************************************************************* 54*91f16700Schasinglulu * BL2 specific defines. 55*91f16700Schasinglulu ******************************************************************************/ 56*91f16700Schasinglulu /* 57*91f16700Schasinglulu * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 58*91f16700Schasinglulu * size plus a little space for growth. 59*91f16700Schasinglulu */ 60*91f16700Schasinglulu #define BL2_BASE STM32MP_BL2_BASE 61*91f16700Schasinglulu #define BL2_LIMIT (STM32MP_BL2_BASE + \ 62*91f16700Schasinglulu STM32MP_BL2_SIZE) 63*91f16700Schasinglulu 64*91f16700Schasinglulu /******************************************************************************* 65*91f16700Schasinglulu * BL33 specific defines. 66*91f16700Schasinglulu ******************************************************************************/ 67*91f16700Schasinglulu #define BL33_BASE STM32MP_BL33_BASE 68*91f16700Schasinglulu 69*91f16700Schasinglulu /******************************************************************************* 70*91f16700Schasinglulu * Platform specific page table and MMU setup constants 71*91f16700Schasinglulu ******************************************************************************/ 72*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) 73*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) 74*91f16700Schasinglulu 75*91f16700Schasinglulu /******************************************************************************* 76*91f16700Schasinglulu * Declarations and constants to access the mailboxes safely. Each mailbox is 77*91f16700Schasinglulu * aligned on the biggest cache line size in the platform. This is known only 78*91f16700Schasinglulu * to the platform as it might have a combination of integrated and external 79*91f16700Schasinglulu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 80*91f16700Schasinglulu * line at any cache level. They could belong to different cpus/clusters & 81*91f16700Schasinglulu * get written while being protected by different locks causing corruption of 82*91f16700Schasinglulu * a valid mailbox address. 83*91f16700Schasinglulu ******************************************************************************/ 84*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT 6 85*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 86*91f16700Schasinglulu 87*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 88