1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2021-2023, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef STM32MP1_FIP_DEF_H 8*91f16700Schasinglulu #define STM32MP1_FIP_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #if STM32MP15_OPTEE_RSV_SHM 11*91f16700Schasinglulu #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 12*91f16700Schasinglulu #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 13*91f16700Schasinglulu #else 14*91f16700Schasinglulu #define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ 15*91f16700Schasinglulu #define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ 16*91f16700Schasinglulu #endif 17*91f16700Schasinglulu 18*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP 19*91f16700Schasinglulu #if STM32MP15 20*91f16700Schasinglulu #define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */ 21*91f16700Schasinglulu #define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */ 22*91f16700Schasinglulu #endif /* STM32MP15 */ 23*91f16700Schasinglulu #else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 24*91f16700Schasinglulu #if STM32MP13 25*91f16700Schasinglulu #if BL2_IN_XIP_MEM 26*91f16700Schasinglulu #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ 27*91f16700Schasinglulu #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ 28*91f16700Schasinglulu #else 29*91f16700Schasinglulu /* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */ 30*91f16700Schasinglulu #define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */ 31*91f16700Schasinglulu /* with 20KB for DTB, SYSRAM is full */ 32*91f16700Schasinglulu #endif 33*91f16700Schasinglulu #endif /* STM32MP13 */ 34*91f16700Schasinglulu #if STM32MP15 35*91f16700Schasinglulu #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ 36*91f16700Schasinglulu #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ 37*91f16700Schasinglulu #endif /* STM32MP15 */ 38*91f16700Schasinglulu #endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 39*91f16700Schasinglulu 40*91f16700Schasinglulu #if STM32MP13 41*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT 42*91f16700Schasinglulu #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 43*91f16700Schasinglulu #else /* TRUSTED_BOARD_BOOT */ 44*91f16700Schasinglulu #define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ 45*91f16700Schasinglulu #endif /* TRUSTED_BOARD_BOOT */ 46*91f16700Schasinglulu #endif /* STM32MP13 */ 47*91f16700Schasinglulu #if STM32MP15 48*91f16700Schasinglulu #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ 49*91f16700Schasinglulu #endif /* STM32MP15 */ 50*91f16700Schasinglulu #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ 51*91f16700Schasinglulu #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 52*91f16700Schasinglulu #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ 53*91f16700Schasinglulu #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ 54*91f16700Schasinglulu 55*91f16700Schasinglulu #if STM32MP13 56*91f16700Schasinglulu #define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ 57*91f16700Schasinglulu STM32MP_BL2_DTB_SIZE) 58*91f16700Schasinglulu #endif /* STM32MP13 */ 59*91f16700Schasinglulu #if STM32MP15 60*91f16700Schasinglulu #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 61*91f16700Schasinglulu STM32MP_SEC_SYSRAM_SIZE - \ 62*91f16700Schasinglulu STM32MP_BL2_SIZE) 63*91f16700Schasinglulu #endif /* STM32MP15 */ 64*91f16700Schasinglulu 65*91f16700Schasinglulu #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 68*91f16700Schasinglulu STM32MP_BL2_RO_SIZE) 69*91f16700Schasinglulu 70*91f16700Schasinglulu #if STM32MP13 71*91f16700Schasinglulu #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 72*91f16700Schasinglulu STM32MP_SYSRAM_SIZE - \ 73*91f16700Schasinglulu STM32MP_BL2_RW_BASE) 74*91f16700Schasinglulu 75*91f16700Schasinglulu #define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE 76*91f16700Schasinglulu #endif /* STM32MP13 */ 77*91f16700Schasinglulu #if STM32MP15 78*91f16700Schasinglulu #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ 79*91f16700Schasinglulu STM32MP_SEC_SYSRAM_SIZE - \ 80*91f16700Schasinglulu STM32MP_BL2_RW_BASE) 81*91f16700Schasinglulu 82*91f16700Schasinglulu #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 83*91f16700Schasinglulu STM32MP_BL2_DTB_SIZE) 84*91f16700Schasinglulu #endif /* STM32MP15 */ 85*91f16700Schasinglulu 86*91f16700Schasinglulu #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE 87*91f16700Schasinglulu 88*91f16700Schasinglulu #define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \ 89*91f16700Schasinglulu STM32MP_BL32_DTB_SIZE) 90*91f16700Schasinglulu 91*91f16700Schasinglulu 92*91f16700Schasinglulu #if defined(IMAGE_BL2) 93*91f16700Schasinglulu #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 94*91f16700Schasinglulu #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 95*91f16700Schasinglulu #endif 96*91f16700Schasinglulu #if defined(IMAGE_BL32) 97*91f16700Schasinglulu #define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE 98*91f16700Schasinglulu #define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE 99*91f16700Schasinglulu #endif 100*91f16700Schasinglulu 101*91f16700Schasinglulu #ifdef AARCH32_SP_OPTEE 102*91f16700Schasinglulu #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 103*91f16700Schasinglulu 104*91f16700Schasinglulu #define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \ 105*91f16700Schasinglulu STM32MP_OPTEE_BASE) 106*91f16700Schasinglulu #endif 107*91f16700Schasinglulu 108*91f16700Schasinglulu #if STM32MP13 109*91f16700Schasinglulu #define STM32MP_FW_CONFIG_BASE SRAM3_BASE 110*91f16700Schasinglulu #endif /* STM32MP13 */ 111*91f16700Schasinglulu #if STM32MP15 112*91f16700Schasinglulu #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ 113*91f16700Schasinglulu STM32MP_SYSRAM_SIZE - \ 114*91f16700Schasinglulu PAGE_SIZE) 115*91f16700Schasinglulu #endif /* STM32MP15 */ 116*91f16700Schasinglulu #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 117*91f16700Schasinglulu STM32MP_BL33_MAX_SIZE) 118*91f16700Schasinglulu 119*91f16700Schasinglulu /* 120*91f16700Schasinglulu * MAX_MMAP_REGIONS is usually: 121*91f16700Schasinglulu * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 122*91f16700Schasinglulu */ 123*91f16700Schasinglulu #if defined(IMAGE_BL32) 124*91f16700Schasinglulu #define MAX_MMAP_REGIONS 10 125*91f16700Schasinglulu #endif 126*91f16700Schasinglulu 127*91f16700Schasinglulu #endif /* STM32MP1_FIP_DEF_H */ 128