1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <errno.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/debug.h> 11*91f16700Schasinglulu #include <drivers/st/bsec.h> 12*91f16700Schasinglulu #include <drivers/st/bsec2_reg.h> 13*91f16700Schasinglulu #include <drivers/st/stm32mp1_rcc.h> 14*91f16700Schasinglulu #include <lib/mmio.h> 15*91f16700Schasinglulu #include <lib/utils_def.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #include <platform_def.h> 18*91f16700Schasinglulu #include <stm32mp1_dbgmcu.h> 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define DBGMCU_IDC U(0x00) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) 23*91f16700Schasinglulu #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) 24*91f16700Schasinglulu #define DBGMCU_IDC_REV_ID_SHIFT 16 25*91f16700Schasinglulu 26*91f16700Schasinglulu static int stm32mp1_dbgmcu_init(void) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu if ((bsec_read_debug_conf() & BSEC_DBGSWGEN) == 0U) { 29*91f16700Schasinglulu INFO("Software access to all debug components is disabled\n"); 30*91f16700Schasinglulu return -1; 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu mmio_setbits_32(RCC_BASE + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 34*91f16700Schasinglulu 35*91f16700Schasinglulu return 0; 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * @brief Get silicon revision from DBGMCU registers. 40*91f16700Schasinglulu * @param chip_version: pointer to the read value. 41*91f16700Schasinglulu * @retval 0 on success, negative value on failure. 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version) 44*91f16700Schasinglulu { 45*91f16700Schasinglulu assert(chip_version != NULL); 46*91f16700Schasinglulu 47*91f16700Schasinglulu if (stm32mp1_dbgmcu_init() != 0) { 48*91f16700Schasinglulu return -EPERM; 49*91f16700Schasinglulu } 50*91f16700Schasinglulu 51*91f16700Schasinglulu *chip_version = (mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & 52*91f16700Schasinglulu DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; 53*91f16700Schasinglulu 54*91f16700Schasinglulu return 0; 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* 58*91f16700Schasinglulu * @brief Get device ID from DBGMCU registers. 59*91f16700Schasinglulu * @param chip_dev_id: pointer to the read value. 60*91f16700Schasinglulu * @retval 0 on success, negative value on failure. 61*91f16700Schasinglulu */ 62*91f16700Schasinglulu int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id) 63*91f16700Schasinglulu { 64*91f16700Schasinglulu assert(chip_dev_id != NULL); 65*91f16700Schasinglulu 66*91f16700Schasinglulu if (stm32mp1_dbgmcu_init() != 0) { 67*91f16700Schasinglulu return -EPERM; 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu *chip_dev_id = mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & 71*91f16700Schasinglulu DBGMCU_IDC_DEV_ID_MASK; 72*91f16700Schasinglulu 73*91f16700Schasinglulu return 0; 74*91f16700Schasinglulu } 75