1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#ifndef STM32MP1_LD_S 8*91f16700Schasinglulu#define STM32MP1_LD_S 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_defs.h> 11*91f16700Schasinglulu#include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700SchasingluluOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 14*91f16700SchasingluluOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 15*91f16700Schasinglulu 16*91f16700SchasingluluENTRY(__BL2_IMAGE_START__) 17*91f16700Schasinglulu 18*91f16700SchasingluluMEMORY { 19*91f16700Schasinglulu HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE 20*91f16700Schasinglulu RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE 21*91f16700Schasinglulu} 22*91f16700Schasinglulu 23*91f16700SchasingluluSECTIONS 24*91f16700Schasinglulu{ 25*91f16700Schasinglulu /* 26*91f16700Schasinglulu * TF mapping must conform to ROM code specification. 27*91f16700Schasinglulu */ 28*91f16700Schasinglulu .header : { 29*91f16700Schasinglulu __HEADER_START__ = .; 30*91f16700Schasinglulu KEEP(*(.header)) 31*91f16700Schasinglulu . = ALIGN(4); 32*91f16700Schasinglulu __HEADER_END__ = .; 33*91f16700Schasinglulu } >HEADER 34*91f16700Schasinglulu 35*91f16700Schasinglulu . = STM32MP_BINARY_BASE; 36*91f16700Schasinglulu .data . : { 37*91f16700Schasinglulu . = ALIGN(PAGE_SIZE); 38*91f16700Schasinglulu __DATA_START__ = .; 39*91f16700Schasinglulu *(.data*) 40*91f16700Schasinglulu 41*91f16700Schasinglulu /* 42*91f16700Schasinglulu * dtb. 43*91f16700Schasinglulu * The strongest and only alignment contraint is MMU 4K page. 44*91f16700Schasinglulu * Indeed as images below will be removed, 4K pages will be re-used. 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); 47*91f16700Schasinglulu __DTB_IMAGE_START__ = .; 48*91f16700Schasinglulu *(.dtb_image*) 49*91f16700Schasinglulu __DTB_IMAGE_END__ = .; 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * bl2. 53*91f16700Schasinglulu * The strongest and only alignment contraint is MMU 4K page. 54*91f16700Schasinglulu * Indeed as images below will be removed, 4K pages will be re-used. 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu#if SEPARATE_CODE_AND_RODATA 57*91f16700Schasinglulu . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE ); 58*91f16700Schasinglulu#else 59*91f16700Schasinglulu . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE ); 60*91f16700Schasinglulu#endif 61*91f16700Schasinglulu __BL2_IMAGE_START__ = .; 62*91f16700Schasinglulu *(.bl2_image*) 63*91f16700Schasinglulu __BL2_IMAGE_END__ = .; 64*91f16700Schasinglulu 65*91f16700Schasinglulu __DATA_END__ = .; 66*91f16700Schasinglulu } >RAM 67*91f16700Schasinglulu 68*91f16700Schasinglulu __TF_END__ = .; 69*91f16700Schasinglulu 70*91f16700Schasinglulu} 71*91f16700Schasinglulu#endif /* STM32MP1_LD_S */ 72