1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <drivers/st/bsec.h> 11*91f16700Schasinglulu #include <drivers/st/bsec2_reg.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <stm32mp1_smc.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include "bsec_svc.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3, 18*91f16700Schasinglulu uint32_t *ret_otp_value) 19*91f16700Schasinglulu { 20*91f16700Schasinglulu uint32_t result; 21*91f16700Schasinglulu uint32_t tmp_data = 0U; 22*91f16700Schasinglulu 23*91f16700Schasinglulu switch (x1) { 24*91f16700Schasinglulu case STM32_SMC_READ_SHADOW: 25*91f16700Schasinglulu result = bsec_read_otp(ret_otp_value, x2); 26*91f16700Schasinglulu break; 27*91f16700Schasinglulu case STM32_SMC_PROG_OTP: 28*91f16700Schasinglulu *ret_otp_value = 0U; 29*91f16700Schasinglulu result = bsec_program_otp(x3, x2); 30*91f16700Schasinglulu break; 31*91f16700Schasinglulu case STM32_SMC_WRITE_SHADOW: 32*91f16700Schasinglulu *ret_otp_value = 0U; 33*91f16700Schasinglulu result = bsec_write_otp(x3, x2); 34*91f16700Schasinglulu break; 35*91f16700Schasinglulu case STM32_SMC_READ_OTP: 36*91f16700Schasinglulu *ret_otp_value = 0U; 37*91f16700Schasinglulu result = bsec_read_otp(&tmp_data, x2); 38*91f16700Schasinglulu if (result != BSEC_OK) { 39*91f16700Schasinglulu break; 40*91f16700Schasinglulu } 41*91f16700Schasinglulu 42*91f16700Schasinglulu result = bsec_shadow_register(x2); 43*91f16700Schasinglulu if (result != BSEC_OK) { 44*91f16700Schasinglulu break; 45*91f16700Schasinglulu } 46*91f16700Schasinglulu 47*91f16700Schasinglulu result = bsec_read_otp(ret_otp_value, x2); 48*91f16700Schasinglulu if (result != BSEC_OK) { 49*91f16700Schasinglulu break; 50*91f16700Schasinglulu } 51*91f16700Schasinglulu 52*91f16700Schasinglulu result = bsec_write_otp(tmp_data, x2); 53*91f16700Schasinglulu break; 54*91f16700Schasinglulu 55*91f16700Schasinglulu default: 56*91f16700Schasinglulu return STM32_SMC_INVALID_PARAMS; 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu return (result == BSEC_OK) ? STM32_SMC_OK : STM32_SMC_FAILED; 60*91f16700Schasinglulu } 61