1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef STM32MP1_SHARED_RESOURCES_H 8*91f16700Schasinglulu #define STM32MP1_SHARED_RESOURCES_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stm32mp_shared_resources.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + (i)) 13*91f16700Schasinglulu 14*91f16700Schasinglulu enum stm32mp_shres { 15*91f16700Schasinglulu STM32MP1_SHRES_CRYP1, 16*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_0, 17*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_1, 18*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_2, 19*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_3, 20*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_4, 21*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_5, 22*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_6, 23*91f16700Schasinglulu STM32MP1_SHRES_GPIOZ_7, 24*91f16700Schasinglulu STM32MP1_SHRES_HASH1, 25*91f16700Schasinglulu STM32MP1_SHRES_I2C4, 26*91f16700Schasinglulu STM32MP1_SHRES_I2C6, 27*91f16700Schasinglulu STM32MP1_SHRES_IWDG1, 28*91f16700Schasinglulu STM32MP1_SHRES_MCU, 29*91f16700Schasinglulu STM32MP1_SHRES_MDMA, 30*91f16700Schasinglulu STM32MP1_SHRES_PLL3, 31*91f16700Schasinglulu STM32MP1_SHRES_RNG1, 32*91f16700Schasinglulu STM32MP1_SHRES_RTC, 33*91f16700Schasinglulu STM32MP1_SHRES_SPI6, 34*91f16700Schasinglulu STM32MP1_SHRES_USART1, 35*91f16700Schasinglulu 36*91f16700Schasinglulu STM32MP1_SHRES_COUNT 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu #endif /* STM32MP1_SHARED_RESOURCES_H */ 39