1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/bl_common.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <drivers/arm/gicv2.h> 10*91f16700Schasinglulu #include <dt-bindings/interrupt-controller/arm-gic.h> 11*91f16700Schasinglulu #include <lib/utils.h> 12*91f16700Schasinglulu #include <libfdt.h> 13*91f16700Schasinglulu #include <plat/common/platform.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <platform_def.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu struct stm32mp_gic_instance { 18*91f16700Schasinglulu uint32_t cells; 19*91f16700Schasinglulu uint32_t phandle_node; 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu /****************************************************************************** 23*91f16700Schasinglulu * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 24*91f16700Schasinglulu * interrupts. 25*91f16700Schasinglulu *****************************************************************************/ 26*91f16700Schasinglulu static const interrupt_prop_t stm32mp_interrupt_props[] = { 27*91f16700Schasinglulu PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 28*91f16700Schasinglulu PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) 29*91f16700Schasinglulu }; 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* Fix target_mask_array as secondary core is not able to initialize it */ 32*91f16700Schasinglulu static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2}; 33*91f16700Schasinglulu 34*91f16700Schasinglulu static gicv2_driver_data_t platform_gic_data = { 35*91f16700Schasinglulu .interrupt_props = stm32mp_interrupt_props, 36*91f16700Schasinglulu .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props), 37*91f16700Schasinglulu .target_masks = target_mask_array, 38*91f16700Schasinglulu .target_masks_num = ARRAY_SIZE(target_mask_array), 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu static struct stm32mp_gic_instance stm32mp_gic; 42*91f16700Schasinglulu 43*91f16700Schasinglulu void stm32mp_gic_init(void) 44*91f16700Schasinglulu { 45*91f16700Schasinglulu int node; 46*91f16700Schasinglulu void *fdt; 47*91f16700Schasinglulu const fdt32_t *cuint; 48*91f16700Schasinglulu struct dt_node_info dt_gic; 49*91f16700Schasinglulu 50*91f16700Schasinglulu if (fdt_get_address(&fdt) == 0) { 51*91f16700Schasinglulu panic(); 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic"); 55*91f16700Schasinglulu if (node < 0) { 56*91f16700Schasinglulu panic(); 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu platform_gic_data.gicd_base = dt_gic.base; 60*91f16700Schasinglulu 61*91f16700Schasinglulu cuint = fdt_getprop(fdt, node, "reg", NULL); 62*91f16700Schasinglulu if (cuint == NULL) { 63*91f16700Schasinglulu panic(); 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2)); 67*91f16700Schasinglulu 68*91f16700Schasinglulu cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL); 69*91f16700Schasinglulu if (cuint == NULL) { 70*91f16700Schasinglulu panic(); 71*91f16700Schasinglulu } 72*91f16700Schasinglulu 73*91f16700Schasinglulu stm32mp_gic.cells = fdt32_to_cpu(*cuint); 74*91f16700Schasinglulu 75*91f16700Schasinglulu stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node); 76*91f16700Schasinglulu if (stm32mp_gic.phandle_node == 0U) { 77*91f16700Schasinglulu panic(); 78*91f16700Schasinglulu } 79*91f16700Schasinglulu 80*91f16700Schasinglulu gicv2_driver_init(&platform_gic_data); 81*91f16700Schasinglulu gicv2_distif_init(); 82*91f16700Schasinglulu 83*91f16700Schasinglulu stm32mp_gic_pcpu_init(); 84*91f16700Schasinglulu } 85*91f16700Schasinglulu 86*91f16700Schasinglulu void stm32mp_gic_pcpu_init(void) 87*91f16700Schasinglulu { 88*91f16700Schasinglulu gicv2_pcpu_distif_init(); 89*91f16700Schasinglulu gicv2_set_pe_target_mask(plat_my_core_pos()); 90*91f16700Schasinglulu gicv2_cpuif_enable(); 91*91f16700Schasinglulu } 92