xref: /arm-trusted-firmware/plat/st/common/include/stm32mp_shared_resources.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef STM32MP_SHARED_RESOURCES_H
8*91f16700Schasinglulu #define STM32MP_SHARED_RESOURCES_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <stdbool.h>
11*91f16700Schasinglulu #include <stdint.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu #ifdef STM32MP_SHARED_RESOURCES
14*91f16700Schasinglulu enum stm32mp_shres;
15*91f16700Schasinglulu 
16*91f16700Schasinglulu /* Return true if @clock_id is shared by secure and non-secure worlds */
17*91f16700Schasinglulu bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
18*91f16700Schasinglulu 
19*91f16700Schasinglulu /* Return true if and only if @reset_id relates to a non-secure peripheral */
20*91f16700Schasinglulu bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
21*91f16700Schasinglulu 
22*91f16700Schasinglulu /* Register a shared resource assigned to the secure world */
23*91f16700Schasinglulu void stm32mp_register_secure_periph(enum stm32mp_shres id);
24*91f16700Schasinglulu 
25*91f16700Schasinglulu /* Register a shared resource assigned to the non-secure world */
26*91f16700Schasinglulu void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
27*91f16700Schasinglulu 
28*91f16700Schasinglulu /* Register a peripheral as secure or non-secure based on IO base address */
29*91f16700Schasinglulu void stm32mp_register_secure_periph_iomem(uintptr_t base);
30*91f16700Schasinglulu void stm32mp_register_non_secure_periph_iomem(uintptr_t base);
31*91f16700Schasinglulu 
32*91f16700Schasinglulu /* Register a GPIO as secure or non-secure based on its bank and pin numbers */
33*91f16700Schasinglulu void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
34*91f16700Schasinglulu void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
35*91f16700Schasinglulu 
36*91f16700Schasinglulu /* Consolidate peripheral states and lock against new peripheral registering */
37*91f16700Schasinglulu void stm32mp_lock_periph_registering(void);
38*91f16700Schasinglulu #else
39*91f16700Schasinglulu static inline void stm32mp_register_secure_periph_iomem(uintptr_t base __unused)
40*91f16700Schasinglulu {
41*91f16700Schasinglulu }
42*91f16700Schasinglulu 
43*91f16700Schasinglulu static inline
44*91f16700Schasinglulu void stm32mp_register_non_secure_periph_iomem(uintptr_t base __unused)
45*91f16700Schasinglulu {
46*91f16700Schasinglulu }
47*91f16700Schasinglulu 
48*91f16700Schasinglulu static inline void stm32mp_register_secure_gpio(unsigned int bank __unused,
49*91f16700Schasinglulu 						unsigned int pin __unused)
50*91f16700Schasinglulu {
51*91f16700Schasinglulu }
52*91f16700Schasinglulu 
53*91f16700Schasinglulu static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused,
54*91f16700Schasinglulu 						    unsigned int pin __unused)
55*91f16700Schasinglulu {
56*91f16700Schasinglulu }
57*91f16700Schasinglulu #endif /* STM32MP_SHARED_RESOURCES */
58*91f16700Schasinglulu #endif /* STM32MP_SHARED_RESOURCES_H */
59