1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <common/debug.h> 12*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 13*91f16700Schasinglulu #include <plat/common/platform.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include "uniphier.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu struct uniphier_reg_region { 18*91f16700Schasinglulu uintptr_t base; 19*91f16700Schasinglulu size_t size; 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu static const struct uniphier_reg_region uniphier_reg_region[] = { 23*91f16700Schasinglulu [UNIPHIER_SOC_LD11] = { 24*91f16700Schasinglulu .base = 0x50000000UL, 25*91f16700Schasinglulu .size = 0x20000000UL, 26*91f16700Schasinglulu }, 27*91f16700Schasinglulu [UNIPHIER_SOC_LD20] = { 28*91f16700Schasinglulu .base = 0x50000000UL, 29*91f16700Schasinglulu .size = 0x20000000UL, 30*91f16700Schasinglulu }, 31*91f16700Schasinglulu [UNIPHIER_SOC_PXS3] = { 32*91f16700Schasinglulu .base = 0x50000000UL, 33*91f16700Schasinglulu .size = 0x20000000UL, 34*91f16700Schasinglulu }, 35*91f16700Schasinglulu }; 36*91f16700Schasinglulu 37*91f16700Schasinglulu void uniphier_mmap_setup(unsigned int soc) 38*91f16700Schasinglulu { 39*91f16700Schasinglulu VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", 40*91f16700Schasinglulu (void *)BL_CODE_BASE, (void *)BL_END); 41*91f16700Schasinglulu mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 42*91f16700Schasinglulu round_up(BL_END, PAGE_SIZE) - BL_CODE_BASE, 43*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE); 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* remap the code section */ 46*91f16700Schasinglulu VERBOSE("Code region: %p - %p\n", 47*91f16700Schasinglulu (void *)BL_CODE_BASE, (void *)BL_CODE_END); 48*91f16700Schasinglulu mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 49*91f16700Schasinglulu round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, 50*91f16700Schasinglulu MT_CODE | MT_SECURE); 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* remap the coherent memory region */ 53*91f16700Schasinglulu VERBOSE("Coherent region: %p - %p\n", 54*91f16700Schasinglulu (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END); 55*91f16700Schasinglulu mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 56*91f16700Schasinglulu BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 57*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* register region */ 60*91f16700Schasinglulu assert(soc < ARRAY_SIZE(uniphier_reg_region)); 61*91f16700Schasinglulu mmap_add_region(uniphier_reg_region[soc].base, 62*91f16700Schasinglulu uniphier_reg_region[soc].base, 63*91f16700Schasinglulu uniphier_reg_region[soc].size, 64*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); 65*91f16700Schasinglulu 66*91f16700Schasinglulu init_xlat_tables(); 67*91f16700Schasinglulu 68*91f16700Schasinglulu enable_mmu(0); 69*91f16700Schasinglulu 70*91f16700Schasinglulu #if PLAT_RO_XLAT_TABLES 71*91f16700Schasinglulu { 72*91f16700Schasinglulu int ret; 73*91f16700Schasinglulu 74*91f16700Schasinglulu ret = xlat_make_tables_readonly(); 75*91f16700Schasinglulu if (ret) { 76*91f16700Schasinglulu ERROR("Failed to make translation tables read-only."); 77*91f16700Schasinglulu plat_error_handler(ret); 78*91f16700Schasinglulu } 79*91f16700Schasinglulu } 80*91f16700Schasinglulu #endif 81*91f16700Schasinglulu } 82