1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <platform_def.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu .global uniphier_calc_core_pos 11*91f16700Schasinglulu .global plat_my_core_pos 12*91f16700Schasinglulu .globl platform_mem_init 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* 15*91f16700Schasinglulu * unsigned int uniphier_calc_core_pos(u_register_t mpidr) 16*91f16700Schasinglulu * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 17*91f16700Schasinglulu */ 18*91f16700Schasinglulufunc uniphier_calc_core_pos 19*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 20*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 21*91f16700Schasinglulu lsr x0, x0, #MPIDR_AFFINITY_BITS 22*91f16700Schasinglulu mov x2, #UNIPHIER_MAX_CPUS_PER_CLUSTER 23*91f16700Schasinglulu madd x0, x0, x2, x1 24*91f16700Schasinglulu ret 25*91f16700Schasingluluendfunc uniphier_calc_core_pos 26*91f16700Schasinglulu 27*91f16700Schasinglulufunc plat_my_core_pos 28*91f16700Schasinglulu mrs x0, mpidr_el1 29*91f16700Schasinglulu b uniphier_calc_core_pos 30*91f16700Schasingluluendfunc plat_my_core_pos 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc platform_mem_init 33*91f16700Schasinglulu ret 34*91f16700Schasingluluendfunc platform_mem_init 35