1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef UNIPHIER_CONSOLE_H 8*91f16700Schasinglulu #define UNIPHIER_CONSOLE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define UNIPHIER_UART_RX 0x00 /* In: Receive buffer */ 11*91f16700Schasinglulu #define UNIPHIER_UART_TX 0x00 /* Out: Transmit buffer */ 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define UNIPHIER_UART_FCR 0x0c /* Char/FIFO Control Register */ 14*91f16700Schasinglulu #define UNIPHIER_UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define UNIPHIER_UART_LCR_MCR 0x10 /* Line/Modem Control Register */ 17*91f16700Schasinglulu #define UNIPHIER_UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 18*91f16700Schasinglulu #define UNIPHIER_UART_LSR 0x14 /* Line Status Register */ 19*91f16700Schasinglulu #define UNIPHIER_UART_LSR_TEMT 0x40 /* Transmitter empty */ 20*91f16700Schasinglulu #define UNIPHIER_UART_LSR_TEMT_BIT 6 /* Transmitter empty */ 21*91f16700Schasinglulu #define UNIPHIER_UART_LSR_THRE_BIT 5 /* Transmit-hold-register empty */ 22*91f16700Schasinglulu #define UNIPHIER_UART_LSR_DR_BIT 0 /* Receiver data ready */ 23*91f16700Schasinglulu #define UNIPHIER_UART_DLR 0x24 /* Divisor Latch Register */ 24*91f16700Schasinglulu 25*91f16700Schasinglulu #endif /* UNIPHIER_CONSOLE_H */ 26