1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define SQ_REG_REGION_BASE 0x20000000ULL 13*91f16700Schasinglulu #define SQ_REG_REGION_SIZE 0x60000000ULL 14*91f16700Schasinglulu 15*91f16700Schasinglulu void sq_mmap_setup(uintptr_t total_base, size_t total_size, 16*91f16700Schasinglulu const struct mmap_region *mmap) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", 19*91f16700Schasinglulu (void *)total_base, (void *)(total_base + total_size)); 20*91f16700Schasinglulu mmap_add_region(total_base, total_base, 21*91f16700Schasinglulu total_size, 22*91f16700Schasinglulu MT_NON_CACHEABLE | MT_RW | MT_SECURE); 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* remap the code section */ 25*91f16700Schasinglulu VERBOSE("Code region: %p - %p\n", 26*91f16700Schasinglulu (void *)BL_CODE_BASE, (void *)BL_CODE_END); 27*91f16700Schasinglulu mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 28*91f16700Schasinglulu round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, 29*91f16700Schasinglulu MT_NON_CACHEABLE | MT_RO | MT_SECURE); 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* Re-map the read-only data section */ 32*91f16700Schasinglulu VERBOSE("Read-only data region: %p - %p\n", 33*91f16700Schasinglulu (void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END); 34*91f16700Schasinglulu mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 35*91f16700Schasinglulu round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE, 36*91f16700Schasinglulu (MT_NON_CACHEABLE | MT_RO | MT_EXECUTE_NEVER | 37*91f16700Schasinglulu MT_SECURE)); 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* remap the coherent memory region */ 40*91f16700Schasinglulu VERBOSE("Coherent region: %p - %p\n", 41*91f16700Schasinglulu (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END); 42*91f16700Schasinglulu mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 43*91f16700Schasinglulu BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 44*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* register region */ 47*91f16700Schasinglulu mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE, 48*91f16700Schasinglulu SQ_REG_REGION_SIZE, 49*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* additional regions if needed */ 52*91f16700Schasinglulu if (mmap) 53*91f16700Schasinglulu mmap_add(mmap); 54*91f16700Schasinglulu 55*91f16700Schasinglulu init_xlat_tables(); 56*91f16700Schasinglulu } 57