1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <bl31/ehf.h> 12*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 13*91f16700Schasinglulu #include <services/spm_mm_partition.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu static const mmap_region_t plat_arm_secure_partition_mmap[] = { 16*91f16700Schasinglulu PLAT_SQ_FLASH_MMAP, 17*91f16700Schasinglulu PLAT_SQ_UART1_MMAP, 18*91f16700Schasinglulu PLAT_SQ_PERIPH_MMAP, 19*91f16700Schasinglulu PLAT_SQ_SP_IMAGE_MMAP, 20*91f16700Schasinglulu PLAT_SP_IMAGE_NS_BUF_MMAP, 21*91f16700Schasinglulu PLAT_SQ_SP_IMAGE_RW_MMAP, 22*91f16700Schasinglulu PLAT_SPM_SPM_BUF_EL0_MMAP, 23*91f16700Schasinglulu {0} 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* 27*91f16700Schasinglulu * Boot information passed to a secure partition during initialisation. Linear 28*91f16700Schasinglulu * indices in MP information will be filled at runtime. 29*91f16700Schasinglulu */ 30*91f16700Schasinglulu static spm_mm_mp_info_t sp_mp_info[] = { 31*91f16700Schasinglulu {0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0}, 32*91f16700Schasinglulu {0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0}, 33*91f16700Schasinglulu {0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0}, 34*91f16700Schasinglulu {0x80000600, 0}, {0x80000601, 0}, {0x80000700, 0}, {0x80000701, 0}, 35*91f16700Schasinglulu {0x80000800, 0}, {0x80000801, 0}, {0x80000900, 0}, {0x80000901, 0}, 36*91f16700Schasinglulu {0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0}, 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu 39*91f16700Schasinglulu const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 40*91f16700Schasinglulu .h.type = PARAM_SP_IMAGE_BOOT_INFO, 41*91f16700Schasinglulu .h.version = VERSION_1, 42*91f16700Schasinglulu .h.size = sizeof(spm_mm_boot_info_t), 43*91f16700Schasinglulu .h.attr = 0, 44*91f16700Schasinglulu .sp_mem_base = BL32_BASE, 45*91f16700Schasinglulu .sp_mem_limit = BL32_LIMIT, 46*91f16700Schasinglulu .sp_image_base = BL32_BASE, 47*91f16700Schasinglulu .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 48*91f16700Schasinglulu .sp_heap_base = PLAT_SQ_SP_HEAP_BASE, 49*91f16700Schasinglulu .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 50*91f16700Schasinglulu .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 51*91f16700Schasinglulu .sp_image_size = PLAT_SQ_SP_IMAGE_SIZE, 52*91f16700Schasinglulu .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 53*91f16700Schasinglulu .sp_heap_size = PLAT_SQ_SP_HEAP_SIZE, 54*91f16700Schasinglulu .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 55*91f16700Schasinglulu .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 56*91f16700Schasinglulu .num_sp_mem_regions = PLAT_SP_IMAGE_NUM_MEM_REGIONS, 57*91f16700Schasinglulu .num_cpus = PLATFORM_CORE_COUNT, 58*91f16700Schasinglulu .mp_info = sp_mp_info, 59*91f16700Schasinglulu }; 60*91f16700Schasinglulu 61*91f16700Schasinglulu const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 62*91f16700Schasinglulu { 63*91f16700Schasinglulu return plat_arm_secure_partition_mmap; 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 67*91f16700Schasinglulu void *cookie) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu return &plat_arm_secure_partition_boot_info; 70*91f16700Schasinglulu } 71*91f16700Schasinglulu 72*91f16700Schasinglulu static ehf_pri_desc_t sq_exceptions[] = { 73*91f16700Schasinglulu EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), 74*91f16700Schasinglulu }; 75*91f16700Schasinglulu EHF_REGISTER_PRIORITIES(sq_exceptions, ARRAY_SIZE(sq_exceptions), PLAT_PRI_BITS); 76