1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .global sq_calc_core_pos 13*91f16700Schasinglulu .global plat_my_core_pos 14*91f16700Schasinglulu .global platform_mem_init 15*91f16700Schasinglulu .global plat_is_my_cpu_primary 16*91f16700Schasinglulu .global plat_secondary_cold_boot_setup 17*91f16700Schasinglulu .global plat_crash_console_init 18*91f16700Schasinglulu .global plat_crash_console_putc 19*91f16700Schasinglulu .global plat_crash_console_flush 20*91f16700Schasinglulu 21*91f16700Schasinglulu/* 22*91f16700Schasinglulu * unsigned int sq_calc_core_pos(u_register_t mpidr) 23*91f16700Schasinglulu * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 24*91f16700Schasinglulu */ 25*91f16700Schasinglulufunc sq_calc_core_pos 26*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 27*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 28*91f16700Schasinglulu add x0, x1, x0, lsr #7 29*91f16700Schasinglulu ret 30*91f16700Schasingluluendfunc sq_calc_core_pos 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc plat_my_core_pos 33*91f16700Schasinglulu mrs x0, mpidr_el1 34*91f16700Schasinglulu b sq_calc_core_pos 35*91f16700Schasingluluendfunc plat_my_core_pos 36*91f16700Schasinglulu 37*91f16700Schasinglulufunc platform_mem_init 38*91f16700Schasinglulu ret 39*91f16700Schasingluluendfunc platform_mem_init 40*91f16700Schasinglulu 41*91f16700Schasinglulu/* 42*91f16700Schasinglulu * Secondary CPUs are placed in a holding pen, waiting for their mailbox 43*91f16700Schasinglulu * to be populated. Note that all CPUs share the same mailbox ; therefore, 44*91f16700Schasinglulu * populating it will release all CPUs from their holding pen. If 45*91f16700Schasinglulu * finer-grained control is needed then this should be handled in the 46*91f16700Schasinglulu * code that secondary CPUs jump to. 47*91f16700Schasinglulu */ 48*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 49*91f16700Schasinglulu#if !RESET_TO_BL31 50*91f16700Schasinglulu mov_imm x0, BL2_MAILBOX_BASE 51*91f16700Schasinglulu ldr x0, [x0] 52*91f16700Schasinglulu#else 53*91f16700Schasinglulu ldr x0, sq_sec_entrypoint 54*91f16700Schasinglulu#endif 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* Wait until the mailbox gets populated */ 57*91f16700Schasinglulupoll_mailbox: 58*91f16700Schasinglulu cbz x0, 1f 59*91f16700Schasinglulu br x0 60*91f16700Schasinglulu1: 61*91f16700Schasinglulu wfe 62*91f16700Schasinglulu b poll_mailbox 63*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 64*91f16700Schasinglulu 65*91f16700Schasinglulu/* 66*91f16700Schasinglulu * Find out whether the current cpu is the primary 67*91f16700Schasinglulu * cpu (applicable only after a cold boot) 68*91f16700Schasinglulu */ 69*91f16700Schasinglulufunc plat_is_my_cpu_primary 70*91f16700Schasinglulu mov x9, x30 71*91f16700Schasinglulu bl plat_my_core_pos 72*91f16700Schasinglulu ldr x1, =SQ_BOOT_CFG_ADDR 73*91f16700Schasinglulu ldr x1, [x1] 74*91f16700Schasinglulu ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ 75*91f16700Schasinglulu #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 76*91f16700Schasinglulu cmp x0, x1 77*91f16700Schasinglulu cset w0, eq 78*91f16700Schasinglulu ret x9 79*91f16700Schasingluluendfunc plat_is_my_cpu_primary 80*91f16700Schasinglulu 81*91f16700Schasinglulu/* 82*91f16700Schasinglulu * int plat_crash_console_init(void) 83*91f16700Schasinglulu * Function to initialize the crash console 84*91f16700Schasinglulu * without a C Runtime to print crash report. 85*91f16700Schasinglulu * Clobber list : x0, x1, x2 86*91f16700Schasinglulu */ 87*91f16700Schasinglulufunc plat_crash_console_init 88*91f16700Schasinglulu mov_imm x0, PLAT_SQ_BOOT_UART_BASE 89*91f16700Schasinglulu mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ 90*91f16700Schasinglulu mov_imm x2, SQ_CONSOLE_BAUDRATE 91*91f16700Schasinglulu b console_pl011_core_init 92*91f16700Schasingluluendfunc plat_crash_console_init 93*91f16700Schasinglulu 94*91f16700Schasinglulu/* 95*91f16700Schasinglulu * int plat_crash_console_putc(int c) 96*91f16700Schasinglulu * Function to print a character on the crash 97*91f16700Schasinglulu * console without a C Runtime. 98*91f16700Schasinglulu * Clobber list : x1, x2 99*91f16700Schasinglulu */ 100*91f16700Schasinglulufunc plat_crash_console_putc 101*91f16700Schasinglulu mov_imm x1, PLAT_SQ_BOOT_UART_BASE 102*91f16700Schasinglulu b console_pl011_core_putc 103*91f16700Schasingluluendfunc plat_crash_console_putc 104*91f16700Schasinglulu 105*91f16700Schasinglulu/* 106*91f16700Schasinglulu * void plat_crash_console_flush(int c) 107*91f16700Schasinglulu * Function to force a write of all buffered 108*91f16700Schasinglulu * data that hasn't been output. 109*91f16700Schasinglulu * Out : void. 110*91f16700Schasinglulu * Clobber list : x0, x1 111*91f16700Schasinglulu */ 112*91f16700Schasinglulufunc plat_crash_console_flush 113*91f16700Schasinglulu mov_imm x0, PLAT_SQ_BOOT_UART_BASE 114*91f16700Schasinglulu b console_pl011_core_flush 115*91f16700Schasingluluendfunc plat_crash_console_flush 116