1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <common/interrupt_props.h> 12*91f16700Schasinglulu #include <drivers/arm/gicv3.h> 13*91f16700Schasinglulu #include <plat/common/platform.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include "sq_common.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 18*91f16700Schasinglulu 19*91f16700Schasinglulu static const interrupt_prop_t sq_interrupt_props[] = { 20*91f16700Schasinglulu /* G0 interrupts */ 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* SGI0 */ 23*91f16700Schasinglulu INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 24*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 25*91f16700Schasinglulu /* SGI6 */ 26*91f16700Schasinglulu INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 27*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* G1S interrupts */ 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* Timer */ 32*91f16700Schasinglulu INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 33*91f16700Schasinglulu GIC_INTR_CFG_LEVEL), 34*91f16700Schasinglulu /* SGI1 */ 35*91f16700Schasinglulu INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 36*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 37*91f16700Schasinglulu /* SGI2 */ 38*91f16700Schasinglulu INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 39*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 40*91f16700Schasinglulu /* SGI3 */ 41*91f16700Schasinglulu INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 42*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 43*91f16700Schasinglulu /* SGI4 */ 44*91f16700Schasinglulu INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 45*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 46*91f16700Schasinglulu /* SGI5 */ 47*91f16700Schasinglulu INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 48*91f16700Schasinglulu GIC_INTR_CFG_EDGE), 49*91f16700Schasinglulu /* SGI7 */ 50*91f16700Schasinglulu INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 51*91f16700Schasinglulu GIC_INTR_CFG_EDGE) 52*91f16700Schasinglulu }; 53*91f16700Schasinglulu 54*91f16700Schasinglulu static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr) 55*91f16700Schasinglulu { 56*91f16700Schasinglulu return plat_core_pos_by_mpidr(mpidr); 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu static const struct gicv3_driver_data sq_gic_driver_data = { 60*91f16700Schasinglulu .gicd_base = PLAT_SQ_GICD_BASE, 61*91f16700Schasinglulu .gicr_base = PLAT_SQ_GICR_BASE, 62*91f16700Schasinglulu .interrupt_props = sq_interrupt_props, 63*91f16700Schasinglulu .interrupt_props_num = ARRAY_SIZE(sq_interrupt_props), 64*91f16700Schasinglulu .rdistif_num = PLATFORM_CORE_COUNT, 65*91f16700Schasinglulu .rdistif_base_addrs = sq_rdistif_base_addrs, 66*91f16700Schasinglulu .mpidr_to_core_pos = sq_mpidr_to_core_pos, 67*91f16700Schasinglulu }; 68*91f16700Schasinglulu 69*91f16700Schasinglulu void sq_gic_driver_init(void) 70*91f16700Schasinglulu { 71*91f16700Schasinglulu gicv3_driver_init(&sq_gic_driver_data); 72*91f16700Schasinglulu } 73*91f16700Schasinglulu 74*91f16700Schasinglulu void sq_gic_init(void) 75*91f16700Schasinglulu { 76*91f16700Schasinglulu gicv3_distif_init(); 77*91f16700Schasinglulu gicv3_rdistif_init(plat_my_core_pos()); 78*91f16700Schasinglulu gicv3_cpuif_enable(plat_my_core_pos()); 79*91f16700Schasinglulu } 80*91f16700Schasinglulu 81*91f16700Schasinglulu void sq_gic_cpuif_enable(void) 82*91f16700Schasinglulu { 83*91f16700Schasinglulu gicv3_cpuif_enable(plat_my_core_pos()); 84*91f16700Schasinglulu } 85*91f16700Schasinglulu 86*91f16700Schasinglulu void sq_gic_cpuif_disable(void) 87*91f16700Schasinglulu { 88*91f16700Schasinglulu gicv3_cpuif_disable(plat_my_core_pos()); 89*91f16700Schasinglulu } 90*91f16700Schasinglulu 91*91f16700Schasinglulu void sq_gic_pcpu_init(void) 92*91f16700Schasinglulu { 93*91f16700Schasinglulu gicv3_rdistif_init(plat_my_core_pos()); 94*91f16700Schasinglulu } 95