1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#ifndef SYNQUACER_PLAT_LD_S__ 8*91f16700Schasinglulu#define SYNQUACER_PLAT_LD_S__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_defs.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM 13*91f16700Schasinglulu 14*91f16700SchasingluluMEMORY { 15*91f16700Schasinglulu SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE 16*91f16700Schasinglulu} 17*91f16700Schasinglulu 18*91f16700SchasingluluSECTIONS 19*91f16700Schasinglulu{ 20*91f16700Schasinglulu /* 21*91f16700Schasinglulu * Put the page tables in secure DRAM so that the PTW can make cacheable 22*91f16700Schasinglulu * accesses, as the core SPM code expects. (The SRAM on SynQuacer does 23*91f16700Schasinglulu * not support inner shareable WBWA mappings so it is mapped normal 24*91f16700Schasinglulu * non-cacheable) 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu .sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { 27*91f16700Schasinglulu *(.sp_xlat_table) 28*91f16700Schasinglulu } >SP_DRAM 29*91f16700Schasinglulu} 30*91f16700Schasinglulu 31*91f16700Schasinglulu#endif /* SYNQUACER_PLAT_LD_S__ */ 32