1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch_helpers.h> 12*91f16700Schasinglulu #include <lib/bakery_lock.h> 13*91f16700Schasinglulu #include <lib/mmio.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <sq_common.h> 16*91f16700Schasinglulu #include "sq_mhu.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* SCP MHU secure channel registers */ 19*91f16700Schasinglulu #define SCP_INTR_S_STAT 0x200 20*91f16700Schasinglulu #define SCP_INTR_S_SET 0x208 21*91f16700Schasinglulu #define SCP_INTR_S_CLEAR 0x210 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* CPU MHU secure channel registers */ 24*91f16700Schasinglulu #define CPU_INTR_S_STAT 0x300 25*91f16700Schasinglulu #define CPU_INTR_S_SET 0x308 26*91f16700Schasinglulu #define CPU_INTR_S_CLEAR 0x310 27*91f16700Schasinglulu 28*91f16700Schasinglulu DEFINE_BAKERY_LOCK(sq_lock); 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* 31*91f16700Schasinglulu * Slot 31 is reserved because the MHU hardware uses this register bit to 32*91f16700Schasinglulu * indicate a non-secure access attempt. The total number of available slots is 33*91f16700Schasinglulu * therefore 31 [30:0]. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu #define MHU_MAX_SLOT_ID 30 36*91f16700Schasinglulu 37*91f16700Schasinglulu void mhu_secure_message_start(unsigned int slot_id) 38*91f16700Schasinglulu { 39*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 40*91f16700Schasinglulu 41*91f16700Schasinglulu bakery_lock_get(&sq_lock); 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* Make sure any previous command has finished */ 44*91f16700Schasinglulu while (mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & 45*91f16700Schasinglulu (1 << slot_id)) 46*91f16700Schasinglulu ; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu void mhu_secure_message_send(unsigned int slot_id) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 52*91f16700Schasinglulu assert(!(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & 53*91f16700Schasinglulu (1 << slot_id))); 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* Send command to SCP */ 56*91f16700Schasinglulu mmio_write_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu uint32_t mhu_secure_message_wait(void) 60*91f16700Schasinglulu { 61*91f16700Schasinglulu uint32_t response; 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* Wait for response from SCP */ 64*91f16700Schasinglulu while (!(response = mmio_read_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_STAT))) 65*91f16700Schasinglulu ; 66*91f16700Schasinglulu 67*91f16700Schasinglulu return response; 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu void mhu_secure_message_end(unsigned int slot_id) 71*91f16700Schasinglulu { 72*91f16700Schasinglulu assert(slot_id <= MHU_MAX_SLOT_ID); 73*91f16700Schasinglulu 74*91f16700Schasinglulu /* 75*91f16700Schasinglulu * Clear any response we got by writing one in the relevant slot bit to 76*91f16700Schasinglulu * the CLEAR register 77*91f16700Schasinglulu */ 78*91f16700Schasinglulu mmio_write_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); 79*91f16700Schasinglulu 80*91f16700Schasinglulu bakery_lock_release(&sq_lock); 81*91f16700Schasinglulu } 82*91f16700Schasinglulu 83*91f16700Schasinglulu void mhu_secure_init(void) 84*91f16700Schasinglulu { 85*91f16700Schasinglulu bakery_lock_init(&sq_lock); 86*91f16700Schasinglulu 87*91f16700Schasinglulu /* 88*91f16700Schasinglulu * The STAT register resets to zero. Ensure it is in the expected state, 89*91f16700Schasinglulu * as a stale or garbage value would make us think it's a message we've 90*91f16700Schasinglulu * already sent. 91*91f16700Schasinglulu */ 92*91f16700Schasinglulu assert(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) == 0); 93*91f16700Schasinglulu } 94*91f16700Schasinglulu 95*91f16700Schasinglulu void plat_sq_pwrc_setup(void) 96*91f16700Schasinglulu { 97*91f16700Schasinglulu mhu_secure_init(); 98*91f16700Schasinglulu } 99