1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu/* 8*91f16700Schasinglulu * armstub8.bin header to let the GPU firmware recognise this code. 9*91f16700Schasinglulu * It will then write the load address of the kernel image and the DT 10*91f16700Schasinglulu * after the header magic in RAM, so we can read those addresses at runtime. 11*91f16700Schasinglulu */ 12*91f16700Schasinglulu 13*91f16700Schasinglulu.text 14*91f16700Schasinglulu b armstub8_end 15*91f16700Schasinglulu 16*91f16700Schasinglulu.global stub_magic 17*91f16700Schasinglulu.global dtb_ptr32 18*91f16700Schasinglulu.global kernel_entry32 19*91f16700Schasinglulu 20*91f16700Schasinglulu.org 0xf0 21*91f16700Schasingluluarmstub8: 22*91f16700Schasinglulustub_magic: 23*91f16700Schasinglulu .word 0x5afe570b 24*91f16700Schasinglulustub_version: 25*91f16700Schasinglulu .word 0 26*91f16700Schasingluludtb_ptr32: 27*91f16700Schasinglulu .word 0x0 28*91f16700Schasinglulukernel_entry32: 29*91f16700Schasinglulu .word 0x0 30*91f16700Schasinglulu 31*91f16700Schasinglulu/* 32*91f16700Schasinglulu * Technically an offset of 0x100 would suffice, but the follow-up code 33*91f16700Schasinglulu * (bl31_entrypoint.S at BL31_BASE) needs to be page aligned, so pad here 34*91f16700Schasinglulu * till the end of the first 4K page. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu.org 0x1000 37*91f16700Schasingluluarmstub8_end: 38